DS90CR485_15 Datasheet, PDF (7/22 Pages) Texas Instruments – 133MHz 48-bit Channel Link Serializer (6.384 Gbps)

DS90CR485
www.ti.com
SNLS143D – FEBRUARY 2003 – REVISED MARCH 2013
DS90CR485 PIN DESCRIPTION—CHANNEL LINK SERIALIZER (continued)
Pin Name I/O
PLLSEL
I
PRE
I
BAL
I
DS_OPT
I
TSEN
O
PRBS_EN I
PAT_SEL
I
CON1
I
CON2
I
CON3
I
CON4
I
CON5 to
I
CON8
TEST1
I
No. of
Pins
1
1
1
1
1
1
1
1
1
1
1
4
Description
LVCMOS/LVTTL level single-ended inputs. Control input for PLL range select. This pin must be tied to V_CC
for 66MHz to 133 MHz operation. No connect or tied to low is reserved for future use. 3V tolerant when
V_CC3V = 3.3V. ⁽¹⁾
LVCMOS/LVTTL level single-ended inputs. Pre-emphasis level select. Pre-emphasis is active when input is
tied to V_CC through external pull-up resistor. Resistor value determines pre-emphasis level (see table in
Applications Information section). For normal LVDS levels (no pre-emphasis), leave this pin open (do not
tie to ground).
3V tolerant when V_CC3V = 3.3V.
LVCMOS/LVTTL level single-ended inputs. TTL level input. Tied this pin to Vcc to enable DC Balance
function. When tied low or left open, the DC Balance function is disabled. Please refer to the Applications
Information on the back for more information. See Figure 9 and Figure 10.
3V tolerant when V_CC3V = 3.3V.
LVCMOS/LVTTL level single-ended inputs. Cable Deskew performed when TTL level input is low. No TxIN
data is sampled during Deskew. To perform Deskew function, input must be held low for a minimum of
4096 clock cycles. The Deskew operation is normally conducted after the TX and RX PLLs have locked. It
should also be conducted after a system reset, or a reconfiguration event. Please refer to the Applications
Information section in back of this datasheet for more information.
3V tolerant when V_CC3V = 3.3V.
Termination Sense pin. The logic state output of this pin reports the presence of a remote termination
resistor. TSEN is LOW when NO termination has been detected. TSEN is HIGH when a termination of
100Ω has been detected.
Note, TSEN pin is an open-collector output, an external pull-up resistor of 1kΩ is required in order for
TSEN pin to function.
PRBS generator enable pin. The Pseudo Random Binary Sequence (PRBS) generator is enable when this
pin is tied High. Tie Low or float to disable the PRBS generator.
3V tolerant when V_CC3V = 3.3V.
PRBS-23 or PRBS-15 mode selection pin. PRBS-23 mode is enabled when this pin is tied High. Tie Low or
float to enable PRBS-15 mode.
3V tolerant when V_CC3V = 3.3V.
Control pin. This pin is reserved for future use. Tied to Low or NC.
Control pin. This pin must be tied High or pulled to high for normal operation Tied to Low for internal
BIST function only. Do not float.
3V tolerant when V_CC3V = 3.3V.
Control pin. This pin must be tied Low to configure the device for specific operation. Tied to High or
floating is reserved for future use.
Control pin. When tied High, all eight LVDS output channels (A0-A7) are enabled. Tied to Low will disable
LVDS output channels A4-A7. Must tie High for standard operation.
3V tolerant when V_CC3V = 3.3V.
Control pins. Tied to Low for normal operation.
1
This pin should be tied low or left open. Tied to high (V_CC) or pulled to high (V_CC) is reserved for future use.
(2)
TEST2
I
1
This pin should be tied low or left open. Tied to high (V_CC) or pulled to high (V_CC) is reserved for future use.
(2)
NC
V_CC
P
GND
G
V_CC3V
P
GND_3V
G
PLLV_CC
P
PLLGND
G
LVDSV_CC
P
LVDSGND G
14 No connect. Make NO Connection to these pins - leave open.
3
2.5V Power supply pins for core logic.
6
Ground pins for 2.5V power supply.
1
3.3V Power supply pin for 3V tolerant input support.⁽³⁾
1
Ground pin for 3.3V power supply.
2
Power supply pins for PLL circuitry. Connect to 2.5V power supply.
3
Ground pins for PLL circuitry.
4
Power supply pins for LVDS outputs. Connect to 2.5V power supply.
5
Ground pins for LVDS outputs.
(2) Inputs default to “low” when left open due to internal pull-down resistor.
(3) V_CC3V pins must proceed power up before other V_CC pins. See Applications Information Section for detail.
Copyright © 2003–2013, Texas Instruments Incorporated
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