DS90CR485_15 Datasheet, PDF (13/22 Pages) Texas Instruments – 133MHz 48-bit Channel Link Serializer (6.384 Gbps)

DS90CR485
www.ti.com
SNLS143D – FEBRUARY 2003 – REVISED MARCH 2013
Note that the deskew initialization must be performed at least once after the PLL has locked to the input clock
frequency, and it must be done at the time when the receiver is powered up and PLL has locked. If power is lost,
or if the cable has been switched or disconnected, the initialization procedure must be repeated or else the
receiver may not sample the incoming LVDS data correctly.
HOW TO CONFIGURE FOR BACKPLANE APPLICATIONS
In a backplane application with differential line impedance of 100Ω the differential line pair-to-pair skew can
controlled by trace layout. In a backplane application with short PCB distance traces, pre-emphasis from the
transmitter is typically not required. The "PRE" pin should be left open (do not tie to ground). A resistor pad
provision for a pull up resistor to V_CC can be implemented in case pre-emphasis is needed to counteract heavy
capacitive loading effects.
HOW TO CONFIGURE FOR CABLE INTERCONNECT APPLICATIONS
In applications that require the long cable drive capability, the DS90CR485 offers higher bandwidth support and
longer cable drive with the use of DC balanced data transmission, pre-emphasis. Cable drive is enhanced with a
user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable
loading effects. This requires the use of one pull-up resistor to V_CC; please refer to Table 2 to set the level
needed. Optional DC balancing on a cycle-to-cycle basis, is also provided to reduce ISI (Inter-Symbol
Interference) for long cable applications. With pre-emphasis and DC balancing, a low distortion eye-pattern is
provided at the receiver end of the cable.
SUPPLY BYPASS RECOMMENDATIONS
Bypass capacitors must be used on the power supply pins. Different pins supply different portions of the circuit,
therefore capacitors should be nearby all power supply pins except as noted in the table. Use high frequency
ceramic (surface mount recommended) 0.1μF capacitors close to each supply pin. If space allows, a 0.01μF
capacitor should be used in parallel, with the smallest value closest to the device pin. Additional scattered
capacitors over the printed circuit board will improve decoupling. Multiple (large) via should be used to connect
the decoupling capacitors to the power plane. A 4.7 to 10μF bulk cap is recommended near the PLLVCC pins
and also the LVDSVCC pins. Connections between the caps and the pin should use wide traces.
INPUT SIGNAL QUALITY REQUIREMENT
The input signal quality must comply to the datasheet requirements, please refer to the Recommended Input
Requirements table for specifications. In addition undershoots in excess of the ABS MAX specifications are not
recommended. If the line between the host device and the transmitter is long and acts as a transmission line,
then termination should be employed. If the transmitter is being driven from a device with programmable drive
strength, data inputs are recommended to be set to a weak setting to prevent transmission line effects. The clock
signal is typically set higher to provide a clean edge that is also low jitter.
LVDS INTERCONNECT GUIDELINES
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings (S = space between the pair, 2S = space between the pairs, 3S = space to
TTL signal)
• Minimize the number of VIA
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Minimize skew between pairs
• Terminate as close to the RX inputs as possible
Copyright © 2003–2013, Texas Instruments Incorporated
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