DS90CR485_15 Datasheet, PDF (14/22 Pages) Texas Instruments – 133MHz 48-bit Channel Link Serializer (6.384 Gbps)

DS90CR485
SNLS143D – FEBRUARY 2003 – REVISED MARCH 2013
Select TX
CR481/3
CR485
Select RX
Select RX
Balance
Mode
CR484
Balance
Mode
Balance
Mode
CR486
Balance
Mode
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DESKEW
Configuration 1
Not supported
Configuration 2
Configuration 3
Configuration 4
DESKEW
Not supported
Configuration 5
Configuration 6
Figure 11. Deskew Configuration Setup Chart
CONFIGURATION 1
DS90CR481/483 and DS90CR484 with DC Balance ON (BAL = High, 33MHz to 80MHz) − The DS_OPT pin at
the input of the transmitter DS90CR481/483 must be applied low for a minimum of four clock cycles in order for
the receiver to complete the deskew operation. The input to the DS_OPT pin can be applied at any time after the
PLL has locked to the input clock frequency. In this particular setup, the "DESKEW" pin on the receiver
DS90CR484 must set High.
CONFIGURATION 2
DS90CR481/483 and DS90CR486 with DC Balance ON (BAL=High, CON1=High, 66MHz to 112MHz) − The
DS_OPT pin at the input of the transmitter DS90CR481/483 can be set to High OR Low when power up. The
period of this input to the DS_OPT pin must be at least 20ms (TX and RX PLLs lock time) plus 4096 clock cycles
in order for the receiver to complete the deskew operation. The "DESKEW" and CON1 pins on the receiver
DS90CR486 must be tied to High for this setup.
CONFIGURATION 3
DS90CR481/483 and DS90CR486 with DC Balance OFF (BAL=Low, CON1=High, 66MHz to 112MHz) − The
input to the DS_OPT pin of the transmitter DS90CR481/483 in this configuration is completely ignored by the
transmitters. In order to initialize the deskew operation on the receiver DS90CR486, data and clock must be
applied to the transmitter when power up. The "DESKEW" and CON1 pins on the receiver DS90CR486 must be
tied to High for this setup.
CONFIGURATION 4
DS90CR485 and DS90CR484 with DC Balance ON (BAL=High, 66MHz to 80MHz) − The DS_OPT pin at the
input of the transmitter DS90CR485 must be applied low for a minimum of four clock cycles in order for the
receiver to complete the deskew operation. The input to the DS_OPT pin can be applied at any time after the
PLL has locked to the input clock frequency. In this setup, the "DESKEW" pin on the receiver DS90CR484 must
set High.
CONFIGURATION 5
DS90CR485 and DS90CR486 with DC Balance ON (DS90CR486’s BAL=Hiigh and CON1=High, 66MHz to
133MHz) − The DS_OPT pin at the input of the transmitter DS90CR485 can be set to High OR Low when power
up. The period of this input to the DS_OPT pin must be at least 20ms (TX and RX PLLs lock time) plus 4096
clock cycles in order for the receiver to complete the deskew operation. The "DESKEW" and CON1 pins on the
receiver DS90CR486 must set High.
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