DS90CR485_15 Datasheet, PDF (4/22 Pages) Texas Instruments – 133MHz 48-bit Channel Link Serializer (6.384 Gbps)

DS90CR485
SNLS143D – FEBRUARY 2003 – REVISED MARCH 2013
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Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified. ⁽¹⁾
Symbol
Parameter
TJCC Transmitter Jitter Cycle-to-Cycle ⁽⁵⁾
Min
f = 133 MHz
f = 100 MHz
f = 66 MHz
BWPLL PLL Bandwidth ≥ 66MHz
TPLLS Transmitter Phase Lock Loop Set (Figure 6)
TPDD Transmitter Powerdown Delay (Figure 7)
TPDL Transmitter Input to Output Latency (Figure 8)
6(TCIP)
Typ
40
45
50
600
7(TCIP)
Max
70
80
100
10
100
8(TCIP)
Units
ps
ps
ps
kHz
ms
ns
ns
(5) The limits are based on bench characterization of the device's jitter response over the power supply voltage range. Output clock jitter is
measured with a cycle-to-cycle jitter of ±10% at a 1µs rate applied to the transmitter’s input clock signal (CLKIN) while data inputs are
switching with internal PRBS generator enabled without DC-Balance. The typical data is measured with a cycle-to-cycle jitter of ±100ps
applied to the transmitter’s input clock signal (CLKIN).
4
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