DS90CR485_15 Datasheet, PDF (11/22 Pages) Texas Instruments – 133MHz 48-bit Channel Link Serializer (6.384 Gbps)

DS90CR485
www.ti.com
SNLS143D – FEBRUARY 2003 – REVISED MARCH 2013
APPLICATIONS INFORMATION
PRE-EMPHASIS
Adds extra current during LVDS logic transition to reduce cable loading effects. Pre-emphasis strength is set via
a DC voltage level applied from min to max (0.75V to V_CC) at the “PRE” pin. A higher input voltage on the ”PRE”
pin increases the magnitude of dynamic current during data transition. The “PRE” pin requires one pull-up
resistor (Rpre) to V_CC in order to set the DC level. There is an internal resistor network, which causes a voltage
drop. Please refer to Table 2 on value of Rpre to set the voltage level.
Depending upon interconnect performance and clock rate, pre-emphasis, DC balance, and deskew
enhancements allow cables 2 to 7 meters in length to be driven.
Rpre
10kΩ or NC
3.5kΩ
1.75KΩ
900Ω
500Ω
50Ω
Table 2. Pre-emphasis with (Rpre)
Effects (Typ)
Standard LVDS
12.5% pre-emphasis
25% pre-emphasis
50% pre-emphasis
75% pre-emphasis
100% pre-emphasis
INFORMATION ON JITTER REJECTION
The transmitter is designed to reject cycle-to-cycle jitter which may be seen at the transmitter input clock. Very
low cycle-to-cycle jitter is passed on to the transmitter outputs. Cycle-to-cycle jitter has been measured over
frequency to be less than 100ps with input step function jitter applied. This significantly reduces the impact of
input clock source jitter and improves the accuracy of data sampling. Transmitter output jitter is effected by
PLLVCC noise and input clock jitter - minimize supply noise and use a low jitter clock source to limit output jitter.
DC BALANCE MODE
DC Balance mode is set when the BAL pin on the transmitter and receiver are tied HIGH - see DS90CR485 PIN
DESCRIPTION—CHANNEL LINK SERIALIZER.
In addition to data information an additional bit is transmitted on every LVDS data signal line during each cycle
as shown in Figure 10. This bit is the DC balance bit (BAL). The purpose of the DC Balance bit is to minimize the
short- and long-term DC bias on the signal lines. This is achieved by selectively sending the data either
unmodified or inverted.
The value of the DC balance bit is calculated from the running word disparity and the data disparity of the current
word to be sent. The data disparity of the current word is calculated by subtracting the number of bits of value 0
from the number of bits value 1 in the current word. Initially, the running word disparity may be any value
between +7 and −6. The running word disparity is the continuous sum of all the modified data disparity values,
where the unmodified data disparity value is the calculated data disparity minus 1 if the data is sent unmodified
and 1 plus the inverse of the calculated data disparity if the data is sent inverted. The value of the running word
disparity saturates at +7 and −6 in DC balance mode. Please refer to Table 3 for DC balance mode operation.
BAL
0
1
1
1
1
1
Table 3. DC Balance mode
Running Word Disparity
X
Positive
Negative
Positive
Negative
Zero
Current Word Disparity
X
Negative/Zero
Positive
Positive
Negative/Zero
X
Data Sent Invert
NO
NO
NO
YES
YES
YES
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