DS90CR485_15 Datasheet, PDF (12/22 Pages) Texas Instruments – 133MHz 48-bit Channel Link Serializer (6.384 Gbps)

DS90CR485
SNLS143D – FEBRUARY 2003 – REVISED MARCH 2013
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TSEN
The TSEN pin reports the presence of a remote termination resistor to the local system. The TSEN pin is an
open-collector output which requires an external pull-up resistor of 1kΩ at 2.5V to function. The logic state output
of this pin determines if there is termination on the far end of the LVDS clock channel. When TSEN is High, a
termination of 100Ω has been detected. When TSEN is Low, no termination has been detected indicating the
likelihood that the cable is unplugged. This pin reports the line status to the local system.
BIST
To facilitate signal quality testing, an internal test pattern generator is provided on chip. This can be useful in
checking signal quality (eye patterns) in the link. The internal BIST function is activated by driving the PRBS_EN
pin High. There are two PRBS patterns available and the selections is control by the logic state of the PAT_SEL
pin. When PAT_SEL is High, the transmitter generate and send out a PRBS-23 pattern. When PAT_SEL is low,
a PRBS-15 pattern will be generated and sent. When PRBS_EN pin is Low, the logic state of the PAT_SEL pin
will be ignored and the transmitter will operate as indicated by the other control and input pins. The transmitter’s
internally generated PRBS patterns are available for users to monitor signal quality via eye-diagrams. Depending
upon external test equipment requirements, compatibility may or may not be possible.
POWER-UP SEQUENCE AND 3V TOLERANT
The DS90CR485 inputs provide an option for 3.3V tolerant. If this is required, the V_CC3V pin must be connected
to a 3.3V rail. Also when power is applied to the transmitter, V_CC3V pin must be applied before or simultaneously
with other power supply pins (2.5V). If 3.3V tolerance is not required, this pin may be tied to the 2.5V rail.
LVDS OUTPUT
This device features a modified LVDS output that provides an internal, 100Ω termination at the source side of the
link to control of reflections. An external termination resistor is required at the far end of the link and should be
placed as close to the receiver inputs as possible to minimize any resulting stub length. Unused LVDS output
channels should be terminated with 100Ω at the transmitter’s output pin.
POWER DOWN
When the Power Down feature is asserted (PD = Low), the current draw through the supply pins is minimized
and the PLL is shut down. The transmitter outputs are in TRI-STATE when in power down mode. The PD pin
should be driven HIGH to enable the device once V_CC is stable.
DESKEW
The receiver will deskew or compensate the fixed interconnect skew between data signals, with respect to the
rising edge of clock, on each of the independent differential pairs (pair-to-pair skew). For a list of deskew ranges,
please refer to the corresponding receiver datasheet for more information.
In order for the deskew function to work properly, it must be initialized or calibrated. The DS90CR486 deskew
can be initialized with any data pattern with a transition over a period of three clock cycles. Therefore, there are
multiple ways to initialize the deskew function depending on the setup configuration. For example, to initialize the
operation of deskew for DS90CR485 and DS90CR486 in DC balance mode, the DS_OPT pin at the input of the
transmitter DS90CR485 can be set High OR Low when power up. The period of this input to the DS_OPT pin
must be at least 20ms (TX and RX PLLs lock time) plus 4096 clock cycles in order for the receiver to complete
the deskew operation. For other configuration setup with DS90CR483 and DS90CR484, please refer to the flow
chart on Figure 11.
The DS_OPT pin at the input of the transmitter (DS90CR485) is used to initiate the deskew calibration pattern.
Depends on the configuration, it can be set High or Low when power up in order for the receiver to complete the
deskew operation. For this reason, the LVDS clock signal with DS_OPT applied high (active data sampling) shall
be 1111000 or 1110000 pattern and the LVDS data lines (TxOUT 0-7) shall be High for one clock cycle and Low
for the next clock cycle. During the deskew operation with DS_OPT applied low, the LVDS clock signal shall be
1111100 or 1100000 pattern. The transmitter will also output a series of 1111000 or 1110000 onto the LVDS
data lines (TxOUT 0-7) during deskew so that the receiver can automatically calibrated the data sampling strobes
at the receiver inputs. Each data channel is deskewed independently and is tuned over a specific range. Please
refer to corresponding receiver datasheet for a list of deskew ranges.
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