DS90CR485_15 Datasheet, PDF (6/22 Pages) Texas Instruments – 133MHz 48-bit Channel Link Serializer (6.384 Gbps)

DS90CR485
SNLS143D – FEBRUARY 2003 – REVISED MARCH 2013
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Figure 6. Phase Lock Loop Set Time (V_CC ≥ 2.37V)
Figure 7. Power Down Delay
Figure 8. Input to Output Latency
Pin Name I/O
D0-D23
I
CLKIN
I
PD
I
TxOUTP
O
TxOUTM
O
CLK1P
O
CLK1M
O
DS90CR485 PIN DESCRIPTION—CHANNEL LINK SERIALIZER
No. of
Pins
Description
24 LVCMOS/LVTTL level single-ended inputs. 3V tolerant when V_CC3V = 3.3V.
Note, external pull-down resistor of 1kΩ is required on all unused input data pins.
1
LVCMOS/LVTTL level clock input. Samples data on both edges. See Figure 5 and Figure 9.
3V tolerant when V_CC3V = 3.3V.
1
LVCMOS/LVTTL level input. PD = low activates the powerdown function and minimizes power dissipation.
3V tolerant when V_CC3V = 3.3V. ⁽¹⁾
8
Positive LVDS differential data output.
8
Negative LVDS differential data output.
1
Positive LVDS differential clock output.
1
Negative LVDS differential clock output.
(1) Inputs default to “low” when left open due to internal pull-down resistor.
6
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