DS90CR485_15 Datasheet, PDF (5/22 Pages) Texas Instruments – 133MHz 48-bit Channel Link Serializer (6.384 Gbps)

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DS90CR485
SNLS143D – FEBRUARY 2003 – REVISED MARCH 2013
AC TIMING DIAGRAMS
The worst case test pattern produces a maximum toggling of digital circuits, LVCMOS/LVTTL I/O.
Figure 1. “Worst Case” Test Pattern
Figure 2. LVDS Output Load and Transition Times
Figure 3. Input Clock Transition Time
Figure 4. Input Clock High/Low Times
Figure 5. Setup/Hold with CLKIN
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