DS90UB940-Q1 Datasheet, PDF (61/84 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

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DS90UB940-Q1
SNLS479A – NOVEMBER 2014 – REVISED JANUARY 2016
Register Maps (continued)
Table 12. Serial Control Bus Registers (continued)
ADD
(hex)
0x41
Register
Name
LINK
ERROR
COUNT
Bit(s) Function
Type
7:5 RESERVED
RW
4
LINK ERROR
RW
COUNT ENABLE
3:0 LINK ERROR
RW
COUNT
0x43 HSCC_
7:5 RESERVED
RW
CONTROL ₄
SPI_MISO_
RW
MODE
3
SPI_CPOL
RW
2:0 HSCC_MODE RW
0x44
ADAPTIVE
EQ BYPASS
7:5
4
3:1
0
0x45
ADAPTIVE
EQ MIN MAX
7:4
3:0
EQ STAGE 1
RW
SELECT VALUE
RESERVED
RW
EQ STAGE 2
RW
SELECT VALUE
ADAPTIVE EQ RW
BYPASS
RESERVED
RW
ADAPTIVE EQ RW
FLOOR VALUE
Default
Description
Value (hex)
0
Reserved
0
Enable serial link data integrity error count
1: Enable error count
0: DISABLE
0x3
Link error count threshold. Counter is pixel clock based. clk0,
clk1 and DCA are monitored for link errors, if error count is
enabled, deserializer loose lock once error count reaches
threshold. If disabled deserilizer loose lock with one error.
0
Reserved
0
SPI MISO pin mode during Reverse SPI mode
During Reverse SPI mode, SPI_MISO is typically an output
signal. For bused SPI applications, it may be necessary to tri-
state the SPI_MISO output if the device is not selected (SPI_SS
= 0).
0 : Always enable SPI_MISO output driver
1 : Tri-state SPI_MISO output if SPI_SS is not asserted (low)
0
SPI Clock Polarity Control
0 : SPI Data driven on Falling clock edge, sampled on Rising
clock edge
1 : SPI Data driven on Rising clock edge, sampled on Falling
clock edge
0
High-Speed Control Channel Mode
Enables high-speed modes for the secondary link back-channel,
allowing higher speed signaling of GPIOs or SPI interface:
These bits indicates the High Speed Control Channel mode of
operation:
000: Normal frame, GPIO mode
001: High Speed GPIO mode, 1 GPIO
010: High Speed GPIO mode, 2 GPIOs
011: High Speed GPIO mode: 4 GPIOs
100: Reserved
101: Reserved
110: High Speed, Forward Channel SPI mode
111: High Speed, Reverse Channel SPI mode
Adaptive Equalizer Bypass register
If PORT1_SEL is set, this register sets port1 AEQ controls
0x3
EQ select value[5:3] - Used if adaptive EQ is bypassed.
0
Reserved
0
EQ select value [2:0] - Used if adaptive EQ is bypassed.
0
0x08
1: Disable adaptive EQ
0: Enable adaptive EQ
Adaptive Equalizer Configuration
If PORT1_SEL is set, this register sets port1 AEQ configuration
Reserved
When AEQ floor is enabled by mode-sel pin or register
(reg_35[5:4]) the starting setting is given by this register.
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