DS90UB940-Q1 Datasheet, PDF (32/84 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

DS90UB940-Q1
SNLS479A – NOVEMBER 2014 – REVISED JANUARY 2016
Deserializer
MCLK
I2S_CLK
I2S_WC
I2S_Dx
System Clock
Bit Clock
Word Select
Data
4
I2S Receiver
Figure 24. I2S Connection Diagram
I2S_WC
I2S_CLK
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I2S_Dx
MSB
LSB MSB
LSB
Figure 25. I2S Frame Timing Diagram
When paired with a DS90UB925Q, the Deserializer I2S interface supports a single I2S data output through
I2S_DA (24-bit video mode), or two I2S data outputs through I2S_DA and I2S_DB (18-bit video mode).
8.3.12.1 I2S Transport Modes
By default, packetized audio is received during video blanking periods in dedicated Data Island Transport frames.
The transport mode is set in the serializer and auto-loaded into the deserializer by default. The audio
configuration may be disabled from control registers if Forward Channel Frame Transport of I2S data is desired.
In frame transport, only I2S_DA is received to the Deserializer. Surround Sound Mode, which transmits all four
I2S data inputs (I2S_D[D:A]), may only be operated in Data Island Transport mode. This mode is only available
when connected to a DS90UB927Q, DS90UB949-Q1, DS90UB947-Q1, or DS90UB929-Q1 serializer. If
connected to a DS90UB925Q serializer, only I2S_DA and I2S_DB may be received.
8.3.12.2 I2S Jitter Cleaning
This device features a standalone PLL to clean the I2S data jitter, supporting high-end car audio systems. If
I2S_CLK frequency is less than 1MHz, this feature must be disabled through register 0x2B[7]. See Table 12.
8.3.12.3 MCLK
The deserializer has an I2S Master Clock Output (MCLK). It supports x1, x2, or x4 of I2S CLK Frequency. When
the I2S PLL is disabled, the MCLK output is off. Table 7 covers the range of I2S sample rates and MCLK
frequencies. By default, all the MCLK output frequencies are x2 of the I2S CLK frequencies. The MCLK
frequencies can also be enabled through the register bits 0x3A[6:4] (I2S DIVSEL), shown in Table 12. To select
desired MCLK frequency, write 0x3A[7], then write to bit [6:4] accordingly.
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