DS90UB940-Q1 Datasheet, PDF (26/84 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

DS90UB940-Q1
SNLS479A – NOVEMBER 2014 – REVISED JANUARY 2016
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8.3.5 LVCMOS VDDIO Option
The 1.8V or 3.3V Inputs and Outputs are powered from a separate VDDIO supply to offer compatibility with
external system interface signals.
NOTE
When configuring the VDDIO power supplies, all the single-ended data and control input
pins for device need to scale together with the same operating VDDIO levels.
8.3.6 Power Down (PDB)
The deserializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by
the host or through the VDDIO, where VDDIO = 3. 0 V to 3.6 V or VDD33. To save power, disable the link when
the display is not needed (PDB = LOW). When the pin is driven by the host, make sure to release it after VDD33
and VDDIO have reached final levels; no external components are required. In the case of driven by the VDDIO
= 3.0 V to 3.6 V or VDD33 directly, a 10kΩ resistor to the VDDIO = 3.0 V to 3.6 V or VDD33, and a >10 µF
capacitor to the GND are required (see Figure 36 Typical Connection Diagram).
8.3.7 Interrupt Pin — Functional Description and Usage (INTB_IN)
The INTB_IN pin is an active low interrupt input pin. This interrupt signal, when configured, will propagate to the
paired serializer. Consult the appropriate Serializer datasheet for details of how to configure this interrupt
functionality.
1. On the Serializer, set register 0xC6[5] = 1 and 0xC6[0] = 1
2. Deserializer INTB_IN (pin 4) is set LOW by some downstream device.
3. Serializer pulls INTB pin LOW. The signal is active LOW, so a LOW indicates an interrupt condition.
4. External controller detects INTB = LOW; to determine interrupt source, read ISR register.
5. A read to ISR will clear the interrupt at the Serializer, releasing INTB.
6. The external controller typically must then access the remote device to determine downstream interrupt
source and clear the interrupt driving the Deserializer INTB_IN. This would be when the downstream device
releases the INTB_IN (pin 4) on the Deserializer. The system is now ready to return to step (2) at next falling
edge of INTB_IN.
8.3.8 General-purpose I/O
8.3.8.1 GPIO[3:0] and D_GPIO[3:0] Configuration
In normal operation, GPIO[3:0] may be used as general purpose IOs in either forward channel (outputs) or back
channel (inputs) mode. GPIO and D_GPIO modes may be configured from the registers (Table 11). The same
registers configure either GPIO or D_GPIO, depending on the status of PORT1_SEL and PORT0_SEL bits
(0x34[1:0]). D_GPIO operation requires 2-lane FPD-Link III mode. Consult the appropriate Serializer datasheet
for details on D_GPIO configuration. Note: if paired with a DS90UB925Q-Q1serializer, the devices must be
configured into 18-bit mode to allow usage of GPIO pins on the serializer. To enable 18-bit mode, set serializer
register 0x12[2] = 1. 18-bit mode will be auto-loaded into the deserializer from the serializer. See Table 3 for
GPIO enable and configuration.
Description
GPIO3 / D_GPIO3
GPIO2 / D_GPIO2
GPIO1 / D_GPIO1
GPIO0 / D_GPIO0
Table 3. GPIO Enable and Configuration
Device
Serializer
Deserializer
Serializer
Deserializer
Serializer
Deserializer
Serializer
Deserializer
Forward Channel
0x0F[3:0] = 0x3
0x1F[3:0] = 0x5
0x0E[7:4] = 0x3
0x1E[7:4] = 0x5
0x0E[3:0] = 0x3
0x1E[3:0] = 0x5
0x0D[3:0] = 0x3
0x1D[3:0] = 0x5
Back Channel
0x0F[3:0] = 0x5
0x1F[3:0] = 0x3
0x0E[7:4] = 0x5
0x1E[7:4] = 0x3
0x0E[3:0] = 0x5
0x1E[3:0] = 0x3
0x0D[3:0] = 0x5
0x1D[3:0] = 0x3
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