DS90UB940-Q1 Datasheet, PDF (24/84 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

DS90UB940-Q1
SNLS479A – NOVEMBER 2014 – REVISED JANUARY 2016
8 Detailed Description
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8.1 Overview
The DS90UB940-Q1 receives a 35-bit symbol over single or dual serial FPD-Link III pairs operating at up to 3.36
Gbp line rate in 1-lane FPD-Link III mode and 2.975 Gbps per lane in 2-lane FPD-Link III mode. The
DS90UB940-Q1 converts this stream into a CSI-2 MIPI Interface (4 data channels + 1 clock, or 8 data channels
+ 2 clocks in replicate mode). The FPD-Link III serial stream contains an embedded clock, video control signals,
audio, GPIOs, I2C, and the DC-balanced video data and audio data which enhance signal quality to support AC
coupling.
The DS90UB940-Q1 is intended for use with the DS90UB949-Q1 or DS90UB947-Q1 Serializers, but is also
backward compatible to the DS90UB925Q-Q1, DS90UB925AQ-Q1, and DS90UB927Q-Q1 FPD-Link III
Serializers.
The DS90UB940-Q1 deserializer attains lock to a data stream without the use of a separate reference clock
source, which greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the
serializer regardless of the data pattern, delivering true automatic “plug and lock” performance. It can lock to the
incoming serial stream without the need of special training patterns or sync characters. The deserializer recovers
the clock and data by extracting the embedded clock information, validating then deserializing the incoming data
stream.
The DS90UB940-Q1 deserializer incorporates an I2C compatible interface. The I2C compatible interface allows
programming of serializer or deserializer devices from a local host controller. In addition, the devices incorporate
a bidirectional control channel (BCC) that allows communication between serializer/deserializer as well as remote
I2C slave devices.
The bidirectional control channel (BCC) is implemented via embedded signaling in the high-speed forward
channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to
serializer). Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial
link from one I2C bus to another. The implementation allows for arbitration with other I2C compatible masters at
either side of the serial link.
8.2 Functional Block Diagram
RIN0+
RIN0-
RIN1+
RIN1-
CMLOUTP
CMLOUTN
PDB
LOCK
PASS
MODE_SEL0
MODE_SEL1
4
D_GPIOx / SPI /
8
I2S / GPIO /
MIPI CSI-2
Outputs
Timing
and
Control
Clock
Gen
I2C
Controller
CLOCK
MIPI CSI-2
Outputs
I2C_SDA
I2C_SCL
IDx
24
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