DS90UB940-Q1 Datasheet, PDF (34/84 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

DS90UB940-Q1
SNLS479A – NOVEMBER 2014 – REVISED JANUARY 2016
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8.3.13 Built-In Self Test (BIST)
An optional At-Speed Built-In Self Test (BIST) feature supports testing of the high speed serial link and the low-
speed back channel without external data connections. This is useful in the prototype stage, equipment
production, in-system test, and system diagnostics.
8.3.13.1 BIST Configuration And Status
The BIST mode is enabled at the deserializer by pin (BISTEN) or BIST configuration register. The test may
select either an external PCLK or the 33 MHz internal Oscillator clock (OSC) frequency in the Serializer. In the
absence of PCLK, the user can select the internal OSC frequency at the deserializer through the BISTC pin or
BIST configuration register.
When BIST is activated at the deserializer, a BIST enable signal is sent to the serializer through the Back
Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test
pattern and monitors it for errors. The deserializer PASS output pin toggles to flag each frame received
containing one or more errors. The serializer also tracks errors indicated by the CRC fields in each back channel
frame.
The BIST status can be monitored real time on the deserializer PASS pin, with each detected error resulting in a
half pixel clock period toggled LOW. After BIST is deactivated, the result of the last test is held on the PASS
output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low
on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width
applied to the deserializer BISTEN pin. LOCK status is valid throughout the entire duration of BIST.
See Figure 26 for the BIST mode flow diagram.
8.3.13.1.1 Sample BIST Sequence
Note: Before BIST can be enabled, D_GPIO0 (pin 19) must be strapped HIGH and D_GPIO[3:1] (pins 16, 17,
and 18) must be strapped LOW.
1. BIST Mode is enabled via the BISTEN pin of Deserializer. The desired clock source is selected through the
deserializer BISTC pin.
2. The serializer is awakened through the back channel if it is not already on. An all-zeros pattern is balanced,
scrambled, randomized, and sent through the FPD-Link III interface to the deserializer. Once the serializer
and the deserializer are in BIST mode and the deserializer acquires LOCK, the PASS pin of the deserializer
goes high and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the
PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can be
monitored and counted to determine the payload error rate per 35 bits.
3. To Stop BIST mode, set the BISTEN pin LOW. The deserializer stops checking the data, and the final test
result is held on the PASS pin. If the test ran error free, the PASS output will remain HIGH. If there one or
more errors were detected, the PASS output will output constant LOW. The PASS output state is held until a
new BIST is run, the device is RESET, or the device is powered down. BIST duration is user-controlled and
may be of any length.
The link returns to normal operation after the deserializer BISTEN pin is low. shows the waveform diagram of a
typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases it
is difficult to generate errors due to the robustness of the link (differential data transmission etc.), thus they may
be introduced by greatly extending the cable length, faulting the interconnect medium, or reducing signal
condition enhancements (Rx Equalization).
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