DS90UB940-Q1 Datasheet, PDF (30/84 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

DS90UB940-Q1
SNLS479A – NOVEMBER 2014 – REVISED JANUARY 2016
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8.3.9.3 Reverse Channel SPI Operation
In Reverse Channel SPI operation, the Deserializer samples the Slave Select (SS), SPI clock (SCLK) into the
internal oscillator clock domain. In addition, upon detection of the active SPI clock edge, the Deserializer
samples the SPI data (MOSI). The SPI data samples are stored in a buffer to be passed to the Serializer over
the back channel. The Deserializer sends SPI information in a back channel frame to the Serializer. In each
back channel frame, the Deserializer sends an indication of the Slave Select value. The Slave Select should be
inactive (high) for at least one back-channel frame period to ensure propagation to the Serializer.
Because data is delivered in separate back channel frames and buffered, the data may be regenerated in
bursts. The following figure (Figure 22) shows an example of the SPI data regeneration when the data arrives in
three back channel frames. The first frame delivered the SS active indication, the second frame delivered the
first three data bits, and the third frame delivers the additional data bits.
DESERIALIZER
SS
SPLK
MOSI
D0
D1
D2
D3
DN
SS
SERIALIZER
SPLK
MOSI
D0
D1
D2
D3
DN
Figure 22. Reverse Channel SPI Write
For Reverse Channel SPI reads, the SPI master must wait for a round-trip response before generating the
sampling edge of the SPI clock. This is similar to operation in Forward channel mode. Note that at most one
data/clock sample will be sent per back channel frame.
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