DS90UB940-Q1 Datasheet, PDF (27/84 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

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DS90UB940-Q1
SNLS479A – NOVEMBER 2014 – REVISED JANUARY 2016
The input value present on GPIO[3:0] or D_GPIO[3:0] may also be read from register, or configured to local
output mode (Table 11).
8.3.8.2 Back Channel Configuration
The D_GPIO[3:0] pins can be configured to obtain different sampling rates depending on the mode as well as
back channel frequency. The mode is controlled by register 0x43 (Table 11). The back channel frequency can be
controlled several ways:
1. Register 0x23[6] sets the divider that controls the back channel frequency based on the internal oscillator.
0x23[6] = 0 sets the divider to 4 and 0x23[6] = 1 sets the divider to 2. As long as BC_HS_CTL (0x23[4]) is
set to 0, the back channel frequency would be either 5 Mbps or 10Mbps based on this bit.
2. Register 0x23[4] enables the high-speed back channel. This can also be pin-strapped via MODE_SEL1
(SeeTable 4). This bit overrides 0x23[6], and sets the divider for the back channel frequency to 1. Setting this
bit to 1 sets the back channel frequency to 20 Mbps.
The back channel frequency has variation of ±20%. Note: The back channel frequency must be set to 5 Mbps
when paired with a DS90UB925Q-Q1, DS90UB925AQ-Q1, or DS90UB927Q-Q1. See Table 4 for details about
configuring the D_GPIOs in various modes.
HSCC_MODE
(0x43[2:0])
000
011
010
001
Mode
Normal
Fast
Fast
Fast
Table 4. Back Channel D_GPIO Effective Frequency
Number of
D_GPIOs
Samples per
Frame
D_GPIO Effective Frequency⁽¹⁾ (kHz)
5 Mbps BC⁽²⁾ 10 Mbps BC⁽³⁾ 20 Mbps BC⁽⁴⁾
4
1
33
66
133
4
6
200
400
800
2
10
333
666
1333
1
15
500
1000
2000
(1) The effective frequency assumes the worst case back channel frequency (-20%) and a 4X sampling rate.
(2) 5 Mbps corresponds to BC FREQ SELECT = 0 & BC_HS_CTL = 0
(3) 10 Mbps corresponds to BC FREQ SELECT = 1 & BC_HS_CTL = 0
(4) 20 Mbps corresponds to BC FREQ SELECT = X & BC_HS_CTL = 1
D_GPIOs
Allowed
D_GPIO[3:0]
D_GPIO[3:0]
D_GPIO[1:0]
D_GPIO0
8.3.8.3 GPIO_REG[8:5] Configuration
GPIO_REG[8:5] are register-only GPIOs and may be programmed as outputs or read as inputs through local
register bits only. Where applicable, these bits are shared with I2S pins and will override I2S input if enabled into
GPIO_REG mode. See Table 5 for GPIO enable and configuration.
Note: Local GPIO value may be configured and read either through local register access, or remote register
access through the Low-Speed Bidirectional Control Channel. Configuration and state of these pins are not
transported from serializer to deserializer as is the case for GPIO[3:0].
Description
GPIO_REG8
GPIO_REG7
GPIO_REG6
GPIO_REG5
Table 5. GPIO_REG and GPIO Local Enable and Configuration
Register Configuration
0x21[7:4] = 0x1
0x21[7:4] = 0x9
0x21[7:4] = 0x3
0x21[3:0] = 0x1
0x21[3:0] = 0x9
0x21[3:0] = 0x3
0x20[7:4] = 0x1
0x20[7:4] = 0x9
0x20[7:4] = 0x3
0x20[3:0] = 0x1
0x20[3:0] = 0x9
0x20[3:0] = 0x3
Function
Output, L
Output, H
Input, Read: 0x6F[0]
Output, L
Output, H
Input, Read: 0x6E[7]
Output, L
Output, H
Input, Read: 0x6E[6]
Output, L
Output, H
Input, Read: 0x6E[5]
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