DS90UB940-Q1 Datasheet, PDF (31/84 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

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DESERIALIZER
SS
SPLK
MOSI
D0
MISO
DS90UB940-Q1
SNLS479A – NOVEMBER 2014 – REVISED JANUARY 2016
D1
RD0
RD1
SS
SERIALIZER
SPLK
D0
MOSI
MISO
RD0
RD1
Figure 23. Reverse Channel SPI Read
For both Reverse Channel SPI writes and reads, the SPI_SS signal should be deasserted for at least one back
channel frame period.
Table 6. SPI SS Deassertion Requirement
Back Channel Frequency
5 Mbps
10 Mbps
20 Mbps
Deassertion Requirement
7.5 µs
3.75 µs
1.875 µs
8.3.10 Backward Compatibility
The DS90UB940-Q1 is also backward compatible to the DS90UB925Q-Q1, DS90UB925AQ-Q1, and
DS90UB927Q-Q1 for PCLK frequencies ranging from 25MHz to 85MHz. Backward compatibility does not need
to be enabled. When paired with a backward compatible device, the Deserializer will auto-detect to 1-lane FPD-
Link III on the primary channel (RIN0±).
8.3.11 Input Equalization
An FPD-Link III input adaptive equalizer provides compensation for transmission medium losses and reduces
medium-induced deterministic jitter. It equalizes up to 15m STP or 50Ω Coaxial cables with 3 connection breaks
at maximum serializer stream payload of 3.36 Gbps.
8.3.12 I2S Audio Interface
This Deserializer features six I2S output pins that, when paired with a compatible serializer, supports surround
sound audio applications. The bit clock (I2S_CLK) supports frequencies between 1MHz and the smaller of
<PCLK/2 or <13MHz. Four I2S data outputs carry two channels of I2S-formatted digital audio each, with each
channel delineated by the word select (I2C_WC) input.
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