TCM4300 Datasheet, PDF (60/69 Pages) Texas Instruments – Advanced RF Cellular Telephone Interface Circuit (ARCTIC )

4.19 DSP Register Map
The register map accessible to the DSP port is shown in Table 4–20 and Table 4–21. There are 14 system
addressable locations. Note that the write address of FIFO B is the same as the read address of FIFO A.
Figure 4-12 details the connection of TCM4300 to an example DSP.
ADDR
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
NAME
WBD
WBDCtrl
RXI
RXQ
TXI
TXQ
FIFO
DlntCtrl
Timing Adj
AGC DAC
AFC DAC
PWR DAC
DStatCtrl
BST Offset
D9
MSB
WBD_LCKD
Sign
Sign
Sign
Sign
MSB
Clear WBD
MSB
MSB
MSB
MSB
TXGO
Table 4–20. DSP Register Map
D8
D7
D6
D5
D4
D3
D2
LSB
WBD_ON
WBD_BW
Reserved
MSB
MSB
MSB
MSB
FIFO A(B) microcontroller to DSP (DSP to microcontroller)
LSB
SDIS Clear-C Send-D Send-F
Reserved
MODE
SCEN
FMVOX FMRXEN
Reserved
IQRXEN
TXEN
LSB
LSB
LSB
OUT1
D1 D0
Reserved
LSB
LSB
LSB
LSB
Reserved
LSB
Reserved
Reserved
Reserved
RXOF ALB
MSB LSB
ADDR
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
Table 4–21. DSP Register Definitions
NAME
CATEGORY
WBD
Wide-band data
WBDCtrl
Wide-band data control
RXI
RXQ
RX channel A/D results
Analog mode: TXI D/A data
TXI
Digital mode: π /4 DQPSK modulator input data
TXQ
Analog mode: TXQ D/A data
Digital mode: Not used
FIFO
FIFO A(B) microcontroller to DSP (DSP to microcontroller)
DIntCtrl
Interrupt control/status
Timing Adj
Symbol timing adjust
AGC DAC
AGC
AFC DAC
AFC
PWR DAC
Power control
DStatCtrl
Miscellaneous status/control
BST Offset
TDM burst offset
R/W
R
R/W
R
W
W
R/(W)
R/W
W
W
W
W
R/W
W
4–25