TCM4300 Datasheet, PDF (10/69 Pages) Texas Instruments – Advanced RF Cellular Telephone Interface Circuit (ARCTIC )

1.4 Terminal Functions
TERMINAL
NAME
NO.
AFC
11
AGC
10
AVDDREF
3
AVDDRX
7
AVDDTX
19
AVSSREF
98
AVSSRX
12
AVSSTX
22
BAT
1
CINT
77
CMCLK
92
CSCLK
93
DINT
49
DSPA0
74
DSPA1
73
DSPA2
72
DSPA3
71
DSPCSL
70
DSPD0
80
DSPD1
81
DSPD2
82
DSPD3
83
DSPD4
84
DSPD5
85
DSPD6
86
DSPD7
87
DSPD8
88
DSPD9
89
† _{Z = high impedance}
I/O
DESCRIPTION
O Automatic frequency control. The AFC DAC output provides the means to adjust
system temperature-compensated reference oscillator (TCXO).
O Automatic gain control. The AGC digital-to-analog converter (DAC) output can be
used to control the gain of system receiver circuits.
— Analog supply voltage for FM receive path. Power applied to AVDDREF powers the
FM receive path circuitry.
— Analog supply voltage for receive path. Power applied to AVDDRX powers the receive
path circuitry.
— Analog supply voltage for transmit path. Power applied to AVDDTX powers the
transmit path circuitry.
— Analog ground for REFCAP
— Analog ground for receive path
— Analog ground for transmit path
I Battery strength monitor. A sample of the battery voltage is applied to BAT, and this
sample monitors the battery strength.
O Controller data interrupt. CINT is the microcontroller data interrupt (active low) signal
that is sent to the DSP. CINT is caused by a microcontroller write to the Send-C
interrupt register location.
O Codec master clock. CMCLK provides a 2.048-MHz clock that is used as the master
clock and bit clock for the speech codec.
O Codec sample clock. CSCLK provides an 8-kHz frame synchronization pulse for the
speech codec. CSCLK is also connected to the DSP for speech sample interrupts.
O Microcontroller interrupt request. DINT is output when the DSP writes to the SEND
DINT register location. DINT can be active high or low according to the levels of the
MTS0 and MTS1 signals.
I DSP 4-bit parallel address bus. DSPA0 through DSPA3 provides the address bus for
the DSP interface. DSPA3 is the MSB, and DSPA0 is the LSB.
I
I/O/Z
DSP chip select (active low). A low signal at DSPCSL enables the specific DSP
addressed.
DSP 10-bit parallel data bus. DSPD0 through DSPD9 provide a 10-bit data bus for the
DSP. DSPD9 is the MSB, and DSPD0 is the LSB.
1–4