TCM4300 Datasheet, PDF (48/69 Pages) Texas Instruments – Advanced RF Cellular Telephone Interface Circuit (ARCTIC )

4.11.5 Phase-Adjustment Strategy
For an IS-54 system in the digital mode, receiver sample timing must be phase adjusted to synchronize the
A/D conversions to optimum sampling points of the received symbols, and to synchronize the mobile unit
timing to the base station timing. This is done by temporarily increasing or decreasing the periods of the
clocks to be adjusted. To avoid undesirable transients, each cycle of the clock being adjusted is altered by
only one period of MCLKIN. A total adjustment equivalent to multiple MCLKIN periods is accomplished by
altering multiple cycles of the clock being adjusted. The number of cycles altered is controlled by internal
counters.
In the TCM4300 there are two clocks which must be adjusted: CMCLK and an internal 9.72-MHz clock from
which SINT is derived. Each of these clocks has an associated counter that counts the number of cycles
that have been lengthened or shortened by one MCLKIN period each and thus detects when the total
adjustment is complete. These counters are shown in Figure 4–6 as Adjust Counter A and Adjust Counter B.
The magnitude of the 2s complement value written to the timing adjustment register determines the number
of cycles of the clocks to be lengthened or shortened by one MCLKIN period each to achieve the total desired
timing adjustment in units of MCLKIN periods. If a negative number is written, the clock periods are
lengthened for the duration of the timing adjustment, resulting in a timing delay. If a positive number is
written, the clock periods are shortened for the duration of the timing adjustment, resulting in a timing
advance.
The divider generates CMCLK normally divides MCLKIN by either 19 or 18. When the CMCLK period is
being lengthened during a timing adjustment, MCLKIN is divided by either 20 or 19. When the CMCLK period
is being shortened, MCLKIN is divided by either 18 or 17 (see subsection 4.11.2). The divider used to
generate a 9.72-MHz clock divides by 4 during normal operation, by 5 when its period is being lengthened
during timing adjustments, and by 3 when its period is being shortened during timing adjustments.
Because CMCLK and the 9.72-MHz internal clock have different periods, and the timing adjustments are
limited to one period of MCLKIN per period of the clock, these clocks take different times to complete the
entire timing adjustment. Because the total adjustment is the same number of MCLKIN periods for both
clocks, the relative phases of the two clocks are the same after the adjustment as they were before.
Both adjust counters reach zero when the adjustment is complete, so there is no need to write to the timing
adjustment register until another timing adjustment is required. For each write to the timing adjustment
register, a single timing adjustment of the direction and magnitude requested is performed.
The output of each adjustment counter is fed to a variable modulus divider. For counter A, there are three
possible moduli, 3, 4, and 5. For counter B there are four possible moduli, 17, 18, 19, and 20.
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