DS92LX1621_14 Datasheet, PDF (6/48 Pages) Texas Instruments – 10 - 50 MHz DC-Balanced Channel Link III Serializer and Deserializer with Bi-Directional Control Channel

DS92LX1621, DS92LX1622
SNLS327I – MAY 2010 – REVISED JANUARY 2014
www.ti.com
DS92LX1622 Deserializer PIN DESCRIPTIONS (continued)
Pin Name
SDA
M/S
Pin No.
2
40
I/O, Type
Input/Output, Open
Drain
Input, LVCMOS w/
pull up
CAD
1
Input, analog
CONTROL AND CONFIGURATION
PDB
29
Input, LVCMOS w/
pull down
LOCK
28
Output, LVCMOS
PASS
31
Output, LVCMOS
RES
BIST MODE
BISTEN
32, 33, 39
-
37
Input, LVCMOS w/
pull down
PASS
31
Output, LVCMOS
Channel Link III INTERFACE
RIN+
35
RIN-
36
POWER AND GROUND
VDDSSCG
4
VDDOR1/2/3
VDDD
VDDR
VDDCML
VDDPLL
VSS
25, 16, 8
13
30
34
38
DAP
Input/Output, CML
Input/Output, CML
Digital Power
Digital Power
Digital Power
Analog Power
Analog Power
Analog Power
Ground
Description
Data line for serial control bus communication
SDA requires an external pull-up resistor to V_DDIO.
I²C Mode Select
M/S = L, Master; device generates and drives the SCL clock line
M/S = H, Slave (default); device accepts SCL clock input
Continuous Address Decoder
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID address
(See Figure 29)
Power down Mode Input Pin.
PDB = H, Receiver is enabled and is ON.
PDB = L, Receiver is in Sleep (Power down mode). When the Receiver is in the
SLEEP state, the LVCMOS Outputs are in TRI-STATE, the PLL is shutdown
and IDD is minimized.
LOCK Status Output Pin.
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL. May be used as Link Status.
When BISTEN = L; Normal operation
PASS is high to indicate no errors are detected. The PASS pin asserts low to
indicate a CRC error was detected on the link.
Reserved.
Pin 39: This pin MUST be tied LOW.
Pins 32, 33: Leave pin open.
BIST Enable Pin.
BISTEN = H, BIST Mode is enabled.
BISTEN = L, BIST Mode is disabled.
PASS Output Pin for BIST mode.
PASS = H, ERROR FREE Transmission
PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
Noninverting differential input, back channel output.
Inverting differential input, back channel output.
SSCG Power, 1.8V ±5%
Power supply must be connect regardless if SSCG function is in operation
TTL Output Buffer Power, The single-ended outputs and control input are
powered from V_DDIO. V_DDIO can be connected to a 1.8V ±5% or 3.3V ±10%
Digital Core Power, 1.8V ±5%
Rx Analog Power, 1.8V ±5%
Bi-Directional Control Channel Driver Power, 1.8V ±5%
PLL Power, 1.8V ±5%
DAP must be grounded. Connect to the ground plane with at least 16 vias.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6
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