DS92LX1621_14 Datasheet, PDF (26/48 Pages) Texas Instruments – 10 - 50 MHz DC-Balanced Channel Link III Serializer and Deserializer with Bi-Directional Control Channel

DS92LX1621, DS92LX1622
SNLS327I – MAY 2010 – REVISED JANUARY 2014
www.ti.com
Bus Activity:
Master
SDA Line S
Slave
Address
7-bit Address 0
Register
Address
Data
P
Bus Activity:
Slave
A
A
A
C
C
C
K
K
K
Figure 25. Write Byte
Bus Activity:
Master
Slave
Address
Register
Address
Slave
Address
SDA Line S
7-bit Address 0
S
7-bit Address 1
Bus Activity:
Slave
A
A
A
C
C
C
K
K
K
Figure 26. Read Byte
Data
N
A
C
K
P
SDA
SCL
START
MSB
1
7-bit Slave Address
2
6
LSB
ACK
R/W
Direction
Bit
Acknowledge
from the Device
MSB
7
8
9
1
Data Byte
2
LSB N/ACK
*Acknowledge
or Not-ACK
8
9
Repeated for the Lower Data Byte
and Additional Data Transfers
STOP
Figure 27. Basic Operation
SDA
SCL
S
START condition, or
START repeat condition
P
STOP condition
Figure 28. START and STOP Conditions
SLAVE CLOCK STRETCHING
In order to communicate and synchronize with remote devices on the I²C bus through the bi-directional control
channel, slave clock stretching must be supported by the I²C master controller/MCU. The chipset utilizes bus
clock stretching (holding the SCL line low) during data transmission; where the I²C slave pulls the SCL line low
prior to the 9th clock of every I²C data transfer (before the ACK signal). The slave device will not control the
clock and only stretches it until the remote peripheral has responded; which is typically in the order of 12 μs
(typical).
26
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: DS92LX1621 DS92LX1622