DS92LX1621_14 Datasheet, PDF (20/48 Pages) Texas Instruments – 10 - 50 MHz DC-Balanced Channel Link III Serializer and Deserializer with Bi-Directional Control Channel

DS92LX1621, DS92LX1622
SNLS327I – MAY 2010 – REVISED JANUARY 2014
Addr
(Hex)
Name
12
GPIO[5] Config
13
General Purpose
Control Reg
Table 1. DS92LX1621 Control Registers (continued)
Bits Field
7:4 RESERVED
3:2 RESERVED
1
GPIO5 DIR
0
GPIO5 EN
GPCR[7]
GPCR[6]
GPCR[5]
7:0
GPCR[4]
GPCR[3]
GPCR[2]
GPCR[1]
GPCR[0]
R/W
Default
Description
0
Reserved
0
Reserved
RW
1
0: Output
1: Input
RW
1
0: TRI-STATE
1: Enabled
RW
0
0: LOW
1: HIGH
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Addr
(Hex)
0
1
2
Name
I²C Device ID
Reset
Reserved
Auto Clock
OSS Select
SSCG
Table 2. DS92LX1622 Control Registers
Bits
Field
7:1 DEVICE ID
0 DES ID
7:3 RESERVED
2 REM_WAKEUP
1 DIGITALRESET0
0 DIGITALRESET1
7:6
5 AUTO_CLOCK
4 OSS_SEL
3:0 SSCG
R/W Default
Description
7-bit address of Deserializer;
RW
0x60h 0x60h
(1100_000X) default
RW
0
0: Device ID is from CAD
1: Register I²C Device ID overrides CAD
0
Reserved
Remote Wake-up Select
1: Enable. Generate remote wakeup signal automatically
RW
0
wake-up the Serializer in Standby mode
0: Disable. Puts the Serializer (M/S = 0) in Standby mode
when Deserializer M/S = 1
RW
0 self clear
1: Resets the device to default register values. Does not
affect device I2C Bus or Device ID
RW 0 self clear 1: Digital Reset, retains all register values
0
Reserved
RW
0
1: Output PCLK or Internal 25 MHz Oscillator clock
0: Only PCLK when valid PCLK present
Output Sleep State Select
RW
0
0: Outputs = TRI-STATE, when LOCK = L
1: Outputs = LOW, when LOCK = L
SSCG Select
0000: Normal Operation, SSCG OFF
0001: fmod (KHz) PCLK/2168, fdev ±0.50%
0010: fmod (KHz) PCLK/2168, fdev ±1.00%
0011: fmod (KHz) PCLK/2168, fdev ±1.50%
0100: fmod (KHz) PCLK/2168, fdev ±2.00%
0101: fmod (KHz) PCLK/1300, fdev ±0.50%
0110: fmod (KHz) PCLK/1300, fdev ±1.00%
0
0111: fmod (KHz) PCLK/1300, fdev ±1.50%
1000: fmod (KHz) PCLK/1300, fdev ±2.00%
1001: fmod (KHz) PCLK/868, fdev ±0.50%
1010: fmod (KHz) PCLK/868, fdev ±1.00%
1011: fmod (KHz) PCLK/868, fdev ±1.50%
1100: fmod (KHz) PCLK/868, fdev ±2.00%
1101: fmod (KHz) PCLK/650, fdev ±0.50%
1110: fmod (KHz) PCLK/650, fdev ±1.00%
1111: fmod (KHz) PCLK/650, fdev +/-1.50%
20
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