DS92LX1621_14 Datasheet, PDF (11/48 Pages) Texas Instruments – 10 - 50 MHz DC-Balanced Channel Link III Serializer and Deserializer with Bi-Directional Control Channel

DS92LX1621, DS92LX1622
www.ti.com
SNLS327I – MAY 2010 – REVISED JANUARY 2014
Deserializer Switching Characteristics^(1)(2)(3)(4)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
t_RCP
Receiver Output Clock Period
t_RCP = t_TCP
t_PDC
PCLK Duty Cycle
Default Registers
SSCG[3:0] = OFF
PCLK
PCLK
20
T
100
45
50
55
t_CLH
LVCMOS Low-to-High Transition V_DDIO: 1.71V to 1.89V or
Time
3.0V to 3.6V, C_L = 8 pF
(lumped load)
PCLK
t_CHL
LVCMOS High-to-Low Transition _{Default Registers (See}
Time
Table 1)⁽⁵⁾
1.3
2.0
2.8
1.3
2.0
2.8
t_CLH
t_CHL
LVCMOS Low-to-High Transition
Time
LVCMOS High-to-Low Transition
Time
V_DDIO: 1.71V to 1.89V or
3.0V to 3.6V, C_L = 8 pF
(lumped load)
Default Registers (See
Table 1)⁽⁶⁾
Deserializer Data
Outputs
1.6
1.6
2.4
3.3
2.4
3.3
t_ROS
t_ROH
ROUT Setup Data to PCLK
ROUT Hold Data to PCLK
V_DDIO: 1.71V to 1.89V or
3.0V to 3.6V, CL = 8pF
(lumped load)
Default Registers ( See
Table 1)
Deserializer Data
Outputs
0.38T
0.38T
0.5T
0.5T
t_DD
Deserializer Delay
Default Registers
Register 0x03h b[0]
(RRFB = 1)
10 MHz-50 MHz
4.571T + 4.571T + 4.571T
8
12
+ 16
t_DDLT
t_RJIT
t_RDJ
Deserializer Data Lock Time
Receiver Input Jitter Tolerance⁽⁷⁾
Receiver Clock Jitter
PCLK
SSCG[3:0] = OFF
10 MHz-50 MHz
50 MHz
10 MHz
50 MHz
10
0.53
300
550
120
250
t_DPJ
Deserializer Period Jitter⁽⁸⁾
PCLK
SSCG[3:0] = OFF
10 MHz
50 MHz
425
600
320
480
t_DCCJ
Deserializer Cycle-to-Cycle Clock PCLK
Jitter ⁽⁹⁾
SSCG[3:0] = OFF
10 MHz
50 MHz
320
500
300
500
fdev
fmod
Spread Spectrum Clocking
Deviation Frequency
Spread Spectrum Clocking
Modulation Frequency
LVCMOS Output Bus
(See Figure 21)
20 MHz-50 MHz
20 MHz-50 MHz
±0.5% to
±2.0%
±9 kHz to
±66 kHz
Units
ns
%
ns
ns
ns
ns
ms
UI
ps
ps
ps
%
kHz
(1) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, T_A = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
(4) t_DCJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
(5) Specification is guaranteed by characterization and is not tested in production.
(6) Specification is guaranteed by design and is not tested in production.
(7) t_RJIT max (0.61 UI) is limited by instrumentation and actual t_RJIT of in-band jitter at low frequency (<2MHz) is greater than 1 UI.
(8) t_DPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.
(9) t_DCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: DS92LX1621 DS92LX1622