DS92LX1621_14 Datasheet, PDF (10/48 Pages) Texas Instruments – 10 - 50 MHz DC-Balanced Channel Link III Serializer and Deserializer with Bi-Directional Control Channel

DS92LX1621, DS92LX1622
SNLS327I – MAY 2010 – REVISED JANUARY 2014
www.ti.com
Recommended Serializer Timing for PCLK⁽¹⁾⁽²⁾
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
t_TCP
t_TCIH
t_TCIL
Transmit Clock Period
Transmit Clock Input High
Time
Transmit Clock Input Low
Time
10 MHz — 50 MHz
20
0.4T
0.4T
T
0.5T
0.5T
t_CLKT
f_osc
PCLK Input Transition Time
Internal oscillator clock
source
0.5
25
Max
100
0.6T
0.6T
3
Units
ns
ns
ns
ns
MHz
(1) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(2) Typical values represent most likely parametric norms at 1.8V or 3.3V, T_A = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
Serializer Switching Characteristics^(1)(2)(3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
t_LHT
CML Low-to-High Transition
Time
RL = 100Ω (See Figure 8)
t_HLT
CML High-to-Low Transition RL = 100Ω
Time
(See Figure 8)
t_DIS
Data Input Setup to PCLK
2.0
Serializer Data Inputs (See Figure 14)
t_DIH
Data Input Hold from PCLK
2.0
t_PLD
Serializer PLL Lock
Time ^{(4) (5)}
RL = 100Ω
t_SD
Serializer Delay
R_T = 100Ω
f = 10-50 MHz
Reg Address 0x03h b[0] (TRFB = 1)
(See Figure 16)
6.386T + 5
t_JIND
Serializer Output
Deterministic Jitter
Serializer output intrinsic deterministic
jitter. Measure with PRBS-7 test
pattern. PCLK = 50 MHz
t_JINR
Serializer Output Random
Jitter
Serializer output intrinsic random jitter
(cycle-cycle). Alternating – 1,0 pattern.
Serializer output peak-to-peak jitter
t_JINT
Peak-to-peak Serializer
Output Jitter
includes deterministic jitter, random
jitter, and jitter transfer from serializer
input. Measure with PRBS-7 test
pattern.
λ_STXBW
Serializer Jitter Transfer
Function -3 dB Bandwidth
PCLK = 50 MHz
Default Registers
δ_STX
Serializer Jitter Transfer
Function
PCLK = 50 MHz
Default Registers
δ_STXf
Serializer Jitter Transfer
PCLK = 50 MHz
Function Peaking Frequency Default Registers
Typ
150
150
1
6.386T +
12
0.13
0.04
0.396
1.9
0.944
500
Max
330
330
2
6.386T +
19.7
Units
ps
ps
ns
ns
ms
ns
UI ⁽⁶⁾
UI ⁽⁶⁾
UI ⁽⁶⁾
MHz
dB
kHz
(1) Typical values represent most likely parametric norms at 1.8V or 3.3V, T_A = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(3) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(4) t_PLD and t_DDLT is the time required by the serializer and deserializer to obtain data lock when exiting power-down state with an active
PCLK.
(5) Specification is guaranteed by design and is not tested in production.
(6) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
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