DS90UB949-Q1 Datasheet, PDF (59/82 Pages) Texas Instruments – 1080p HDMI to FPD-Link III Bridge Serializer

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DS90UB949-Q1
SNLS452 – NOVEMBER 2014
Register Maps (continued)
ADD
(dec)
96
ADD
(hex)
0x60
Register Name
SPI_TIMING1
97
0x61 SPI_TIMING2
98
0x62 SPI_CONFIG
Bit(s)
7:4
3:0
7:4
3:0
7:2
1
0
Table 10. Serial Control Bus Registers (continued)
Register
Type
RW
RW
RW
R
RW
Default
(hex)
0x02
0x02
0x00
0x00
Function
Description
SPI_HOLD
SPI Data Hold from SPI clock: These bits set the minimum hold time for SPI data
following the SPI clock sampling edge. In addition, this also sets the minimum active
pulse width for the SPI output clock.
0: Do not use.
0x1-0xF: Hold = (SPI_HOLD + 1) * 40ns.
For example, default setting of 2 will result in 120ns data hold time.
SPI_SETUP
SPI Data Setup to SPI Clock: These bits set the minimum setup time for SPI data to the
SPI clock active edge. In addition, this also sets the minimum inactive width for the SPI
output clock.
0: Do not use.
0x1-0xF: Hold = (SPI_SETUP + 1) * 40ns.
For example, default setting of 2 will result in 120ns data setup time.
Reserved.
SPI_SS_SETU SPI Slave Select Setup: This field controls the delay from assertion of the Slave Select
P
low to initial data timing. Delays are in units of 40ns.
Delay = (SPI_SS_SETUP + 1) * 40ns.
Reserved.
SPI_CPHA
SPI Clock Phase setting: Determines which phase of the SPI clock is used for sampling
data.
0: Data sampled on leading (first) clock edge.
1: Data sampled on trailing (second) clock edge.
This bit is read-only, with a value of 0. There is no support for CPHA of 1.
SPI_CPOL
SPI Clock Polarity setting: Determines the base (inactive) value of the SPI clock.
0: base value of the clock is 0.
1: base value of the clock is 1.
This bit affects both capture and propagation of SPI signals.
Copyright © 2014, Texas Instruments Incorporated
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