DS90UB949-Q1 Datasheet, PDF (31/82 Pages) Texas Instruments – 1080p HDMI to FPD-Link III Bridge Serializer

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DS90UB949-Q1
SNLS452 – NOVEMBER 2014
8.3.20.4 External Timing
In external timing mode, the Pattern Generator passes the incoming DE, HS, and VS signals unmodified to the
video control outputs after a two pixel clock delay. It extracts the active frame dimensions from the incoming
signals in order to properly scale the brightness patterns. If the incoming video stream does not use the VS
signal, the Pattern Generator determines the Vertical Blank time by detecting a long period of pixel clocks without
DE asserted.
8.3.20.5 Pattern Inversion
The Pattern Generator also incorporates a global inversion control, located in the PGCFG register, which causes
the output pattern to be bitwise-inverted. For example, the full screen Red pattern becomes full-screen cyan, and
the Vertically Scaled Black to Green pattern becomes Vertically Scaled White to Magenta.
8.3.20.6 Auto Scrolling
The Pattern Generator supports an Auto-Scrolling mode, in which the output pattern cycles through a list of
enabled pattern types. A sequence of up to 16 patterns may be defined in the registers. The patterns may
appear in any order in the sequence and may also appear more than once.
8.3.20.7 Additional Features
Additional pattern generator features can be accessed through the Pattern Generator Indirect Register Map. It
consists of the Pattern Generator Indirect Address (PGIA reg_0x66 — Table 10) and the Pattern Generator
Indirect Data (PGID reg_0x67 — Table 10). See Application Note AN-2198.
8.3.21 Spread Spectrum Clock Tolerance
The DS90UB949-Q1 (for DVI mode) tolerates a spread spectrum input clock to help reduce EMI. The following
triangular SSC profile is supported:
• Frequency deviation ≤2.5%
• Modulation rate ≤ 100kHz
Note: Maximum frequency deviation and maximum modulation rate are not supported simultaneously. Some
typical examples:
• Frequency deviation: 2.5%, modulation rate: 50kHz
• Frequency deviation: 1.25%, modulation rate: 100kHz
8.4 Device Functional Modes
8.4.1 Mode Select Configuration Settings (MODE_SEL[1:0])
Configuration of the device may be done via the MODE_SEL[1:0] input pins, or via the configuration register bits.
A pull-up resistor and a pull-down resistor of suggested values may be used to set the voltage ratio of the
MODE_SEL[1:0] inputs. See Table 7 and Table 8. These values will be latched into register location during
power-up:
Mode
EDID_SEL: Display ID Select
AUTO-SS: Auto Sleep-State
AUX_I2S: AUX Audio Channel
EXT_CTL: External Controller
Override
Table 6. MODE_SEL[1:0] Settings
Setting
0
1
0
1
0
1
0
1
Function
Look for remote EDID, if none found, use internal SRAM EDID. Can be overridden
from register. Remote EDID address may be overridden from default 0xA0.
Use external local EDID.
Disable.
Enable.
HDMI audio.
HDMI + AUX audio channel.
Internal HDMI control.
External HDMI control from I2C interface pins.
Copyright © 2014, Texas Instruments Incorporated
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