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| DS90UB949-Q1 Datasheet, PDF (34/82 Pages) Texas Instruments – 1080p HDMI to FPD-Link III Bridge Serializer | |||
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DS90UB949-Q1
SNLS452 â NOVEMBER 2014
Programming (continued)
HOST
SCL
SDA
VDD18
VDDI2C
R1
VR2
IDx
4.7k
4.7k
R2
SER
SCL
SDA
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Figure 21. Serial Control Bus Connection
The serial control bus consists of two signals, SCL and SDA. SCL is a Serial Bus Clock Input. SDA is the Serial
Bus Data Input / Output signal. Both SCL and SDA signals require an external pull-up resistor to VDD18 or VDD33.
For most applications, a 4.7k⦠pull-up resistor is recommended. However, the pull-up resistor value may be
adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven Low.
The IDx pin configures the control interface to one of 8 possible device addresses. A pull-up resistor and a pull-
down resistor may be used to set the appropriate voltage on the IDx input pin See Table 10 below.
#
Ratio
VR2 / VDD18
1
0
2
0.208
3
0.323
4
0.440
5
0.553
6
0.668
7
0.789
8
1
Table 9. Serial Control Bus Addresses For IDx
Ideal VR2
(V)
0
0.374
0.582
0.792
0.995
1.202
1.420
1.8
Suggested Resistor Suggested Resistor
R1 k⦠(1% tol)
R2 k⦠(1% tol)
OPEN
40.2
118
30.9
107
51.1
113
88.7
82.5
102
68.1
137
56.2
210
13.3
OPEN
7-Bit Address
0x0C
0x0E
0x10
0x12
0x14
0x16
0x18
0x1A
8-Bit Address
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See
Figure 22
SDA
SCL
S
START condition, or
START repeat condition
P
STOP condition
Figure 22. Start And Stop Conditions
To communicate with an I2C slave, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
34
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