DS90UB949-Q1 Datasheet, PDF (56/82 Pages) Texas Instruments – 1080p HDMI to FPD-Link III Bridge Serializer

DS90UB949-Q1
SNLS452 – NOVEMBER 2014
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Register Maps (continued)
ADD
(dec)
85
ADD
(hex)
0x55
Register Name
AUDIO_CFG
90
0x5A DUAL_STS
Bit(s)
7
6
5:4
3
2
1
0
7
6
5:4
3
2
1
0
Table 10. Serial Control Bus Registers (continued)
Register
Type
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
Default
(hex)
0x00
0x0C
0x00
Function
Description
TDM_2_PARA Enable I2S TDM to parallel audio conversion: When this bit is set, the i2s tdm to parallel
LLEL
conversion module is enabled. The clock output from the i2s tdm to parallel conversion
module is them used to send data to the deserializer.
HDMI_I2S_OU HDMI Audio Output Enable: When this bit is set, the HDMI I2S audio data will be output
T
on the I2S audio interface pins. This control is ignored if the
BRIDGE_CFG:AUDIO_MODE is not set to 00 (HDMI audio only).
Reserved.
RST_ON_TYP Reset Audio FIFO on Type Change: When this bit is set, the internal bridge control
E
function will reset the HDMI Audio FIFO on a change in the Audio type.
RST_ON_AIF Reset Audio FIFO on Audio Infoframe: When this bit is set, the internal bridge control
function will reset the HDMI Audio FIFO on a change in the Audio Infoframe checksum.
RST_ON_AVI Reset Audio FIFO on Audio Video Information Infoframe: When this bit is set, the internal
bridge control function will reset the HDMI Audio FIFO on a change in the Audio Video
Information Infoframe checksum.
RST_ON_ACR Reset Audio FIFO on Audio Control Frame: When this bit is set, the internal bridge
control function will reset the HDMI Audio FIFO on a change in the Audio Control Frame
N or CTS fields.
FPD3_LINK_R This bit indicates that the FPD-Link III has detected a valid downstream connection and
DY
determined capabilities for the downstream link.
FPD3_TX_ST
S
FPD-Link III transmit status:
This bit indicates that the FPD-Link III transmitter is active and the receiver is LOCKED to
the transmit clock. It is only asserted once a valid input has been detected, and the FPD-
Link III transmit connection has entered the correct mode (Single vs. Dual mode).
FPD3_PORT_
STS
FPD3 Port Status: If FPD3_TX_STS is set to a 1, this field indicates the port mode status
as follows:
00: Dual FPD-Link III Transmitter mode.
01: Single FPD-Link III Transmit on port 0.
10: Single FPD-Link III Transmit on port 1.
11: Replicate FPD-Link III Transmit on both ports.
TMDS_VALID HDMI TMDS Valid: This bit indicates the TMDS interface is recovering valid TMDS data
from HDMI. In revA1 silicon, this bit will always return 1.
HDMI_PLL_LO HDMI PLL lock status: Indicates the HDMI PLL has locked to the incoming HDMI clock.
CK
NO_HDMI_CL No HDMI Clock Detected: This bit indicates the Frequency Detect circuit did not detect an
K
HDMI clock greater than the value specified in the FREQ_LOW register.
FREQ_STABL HDMI Frequency is Stable: Indicates the Frequency Detection circuit has detected a
E
stable HDMI clock frequency.
56
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