DS90UB949-Q1 Datasheet, PDF (4/82 Pages) Texas Instruments – 1080p HDMI to FPD-Link III Bridge Serializer

DS90UB949-Q1
SNLS452 – NOVEMBER 2014
www.ti.com
Pin Functions (continued)
NAME
PIN
NO.
I/O, TYPE
DESCRIPTION
CEC
1
IO, Open- Consumer Electronic Control Channel Input/Output Interface.
Drain
Pull-up with a 27kΩ resistor to 3.3V
X1
39
I, LVCMOS Optional Oscillator Input: This pin is the optional reference clock for CEC. It must be
connected to a 25 MHz 0.1% (1000ppm), 45-55% duty cycle clock source at CMOS-level
1.8V. Leave it open if unused.
FPD-LINK III SERIAL
DOUT0-
26
O
FPD-Link III Inverting Output 0
The output must be AC-coupled with a 0.1µF capacitor for interfacing with 92x deserializers
and 33nF capacitor for 94x deserializers
DOUT0+
27
O
FPD-Link III True Output 0
The output must be AC-coupled with a 0.1µF capacitor for interfacing with 92x deserializers
and 33nF capacitor for 94x deserializers
DOUT1-
22
O
FPD-Link III Inverting Output 1
The output must be AC-coupled with a 0.1µF capacitor for interfacing with 92x deserializers
and 33nF capacitor for 94x deserializers
DOUT1+
23
O
FPD-Link III True Output 1
The output must be AC-coupled with a 0.1µF capacitor for interfacing with 92x deserializers
and 33nF capacitor for 94x deserializers
LFT
20
Analog FPD-Link III Loop Filter
Connect to a 10nF capacitor to GND
CONTROL
SDA
14
IO, Open- I2C Data Input / Output Interface
Drain
Open drain. Must have an external pull-up to resistor to 1.8V or 3.3V. See I2CSEL pin. DO
NOT FLOAT.
Recommended pull-up: 4.7kΩ.
SCL
15
IO, Open- I2C Clock Input / Output Interface
Drain
Open drain. Must have an external pull-up resistor to 1.8V or 3.3V. See I2CSEL pin. DO
NOT FLOAT.
Recommended pull-up: 4.7kΩ.
I2CSEL
6
I, LVCMOS I2C Voltage Level Strap Option
Tie to V_DDIO with a 10kΩ resistor for 1.8V I2C operation.
Leave floating for 3.3V I2C operation.
This pin is read as an input at power up.
IDx
19
Analog I2C Serial Control Bus Device ID Address Select
MODE_SEL0
18
Analog Mode Select 0. See Table 6.
MODE_SEL1
32
Analog Mode Select 1. See Table 6.
PDB
31
I, LVCMOS Power-Down Mode Input Pin
INTB
13
O, Open- Open Drain. Remote interrupt. Active LOW.
Drain
Pull up to VDDIO with a 4.7kΩ resistor.
REM_INTB
40
O, Open- Remote interrupt. Mirrors status of INTB_IN from the deserializer.
Drain
Note: External pull-up to 1.8V required. Recommended pull-up: 4.7kΩ.
INTB = H, Normal Operation
INTB = L, Interrupt Request
SPI PINS (DUAL LINK MODE ONLY)
MOSI
8
IO, LVCMOS SPI Master Out Slave In. Shared with D_GPIO0
MISO
10
IO, LVCMOS SPI Master In Slave Out. Shared with D_GPIO1
SPLK
11
IO, LVCMOS SPI Clock. Shared with D_GPIO2
SS
12
IO, LVCMOS SPI Slave Select. Shared with D_GPIO3
HIGH SPEED (HS) BIDIRECTIONAL CONTROL CHANNEL GPIO PINS (DUAL LINK MODE ONLY)
D_GPIO0
8
IO, LVCMOS HS GPIO0. Shared with MOSI
D_GPIO1
10
IO, LVCMOS HS GPIO1. Shared with MISO
D_GPIO2
11
IO, LVCMOS HS GPIO2. Shared with SPLK
D_GPIO3
12
IO, LVCMOS HS GPIO3. Shared with SS
4
Submit Documentation Feedback
Product Folder Links: DS90UB949-Q1
Copyright © 2014, Texas Instruments Incorporated