DS90UB949-Q1 Datasheet, PDF (47/82 Pages) Texas Instruments – 1080p HDMI to FPD-Link III Bridge Serializer

www.ti.com
DS90UB949-Q1
SNLS452 – NOVEMBER 2014
Register Maps (continued)
ADD
(dec)
24
ADD
(hex)
0x18
Register Name
SCL High Time
25
0x19 SCL Low Time
26
0x1A Data Path
Control 2
27
0x1B BIST BC Error
Count
Bit(s)
7:0
7:0
7:4
3
2
1
0
7:0
Table 10. Serial Control Bus Registers (continued)
Register
Type
RW
RW
R
RW
RW
R
Default
(hex)
0x7F
0x7F
Strap
0x01
0x00
Function
Description
TX_SCL_HIGH I2C Master SCL high time:
This field configures the high pulse width of the SCL output when the Serializer is the
Master on the local I2C bus. Units are 40 ns for the nominal oscillator clock frequency.
The default value is set to provide a minimum 5us SCL high time with the internal
oscillator clock running at 26.25MHz rather than the nominal 25MHz. Delay includes 5
additional oscillator clock periods.
Min_delay = 38.0952ns * (TX_SCL_HIGH + 5).
TX_SCL_LOW
I2C Master SCL low time:
This field configures the low pulse width of the SCL output when the Serializer is the
Master on the local I2C bus. This value is also used as the SDA setup time by the I2C
Slave for providing data prior to releasing SCL during accesses over the Bidirectional
Control Channel. Units are 40 ns for the nominal oscillator clock frequency. The default
value is set to provide a minimum 5us SCL low time with the internal oscillator clock
running at 26.25MHz rather than the nominal 25MHz. Delay includes 5 additional clock
periods.
Min_delay = 38.0952ns * (TX_SCL_LOW + 5).
Reserved.
SECONDARY
_AUDIO
Enable Secondary Audio.
This register indicates that the AUX audio channel is enabled. The control for this
function is via the AUX_AUDIO bit in the BRIDGE_CFG register register offset 0x54).
The AUX_AUDIO control is strapped from the MODE_SEL0 pin at power-up.
Reserved.
MODE_28B
Enable 28-bit Serializer Mode.
0: 24-bit high-speed data + 3 low-speed control (DE, HS, VS).
1: 28-bit high-speed data mode.
I2S Surround
Enable 5.1- or 7.1-channel I2S audio transport:
0: 2-channel or 4-channel I2S audio is enabled as configured in register 0x12 bits 3 and 0
(default).
1: 5.1- or 7.1-channel audio is enabled.
Note that I2S Data Island Transport is the only option for surround audio. Also note that
in a repeater, this bit may be overridden by the in-band I2S mode detection.
BIST BC Error
Port0/Port1
BIST back channel CRC error counter.
This register stores the back channel CRC error count during BIST Mode (saturates at
255 errors). Clears when a new BIST is initiated or by 0x04[5].
If PORT1_SEL is set, this register indicates Port1 status.
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: DS90UB949-Q1
Submit Documentation Feedback
47