DS90UH929-Q1 Datasheet, PDF (58/77 Pages) Texas Instruments – 720p HDMI to FPD-Link III Bridge Serializer with HDCP

DS90UH929-Q1
SNLS458 – NOVEMBER 2014
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Register Maps (continued)
ADD
(dec)
196
ADD
(hex)
0xC4
Register Name
HDCP_STS
198
0xC6 ICR
Bit(s)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Table 8. Serial Control Bus Registers (continued)
Register
Type
R
R
R
R
R
R
R
R
RW
RW
RW
RW
RW
RW
RW
RW
Default
(hex)
0x00
0x00
Function
Description
I2C_ERR_DET HDCP I2C Error Detected: This bit indicates an error was detected on the embedded
communications channel with the HDCP Receiver. Setting of this bit might indicate that a
problem exists on the link between the HDCP Transmitter and HDCP Receiver. This bit
will be cleared on read.
RX_INT
RX Interrupt : Status of the RX Interrupt signal. The signal is received from the attached
HDCP Receiver and is the status on the INTB_IN pin of the HDCP Receiver. The signal
is active low, so a 0 indicates an interrupt condition.
RX_LOCK_DE Receiver Lock Detect : This bit indicates that the downstream Receiver has indicated
T
Receive Lock to incoming serial data.
DOWN_HPD Downstream Hot Plug Detect: This bit indicates a downstream repeater has reported a
Hot Plug event, indicating addition of a new receiver. This bit will be cleared on read.
RX_DETECT Receiver Detect : This bit indicates that a downstream Receiver has been detected.
KSV_LIST_RD
Y
HDCP Repeater KSV List Ready : This bit indicates that the Receiver KSV list has been
read and is available in the KSV_FIFO registers. The device will wait for the controller to
set the KSV_LIST_VALID bit in the HDCP_CTL register before continuing. This bit will be
cleared once the controller sets the KSV_LIST_VALID bit.
KSV_RDY
HDCP Receiver KSV Ready : This bit indicates that the Receiver KSV has been read and
is available in the HDCP_BKSV registers. If the de-vice is not a Repeater, it will wait for
the controller to set the KSV_VALID bit in the HDCP_CTL register before continuing. This
bit will be cleared once the controller sets the KSV_VALID bit.
AUTHED
HDCP Authenticated: Indicates the HDCP authentication has completed successfully.
The controller may now send video data re-quiring content protection. This bit will be
cleared if authentication is lost or if the controller restarts authentication.
IE_IND_ACC Interrupt on Indirect Access Complete: Enables interrupt on completion of Indirect
Register Access.
IE_RXDET_IN Interrupt on Receiver Detect: Enables interrupt on detection of a downstream Receiver. If
T
HDCP_CFG:RX_DET_SEL is set to a 1, the interrupt will wait for Receiver Lock Detect.
IE_RX_INT
Interrupt on Receiver interrupt: Enables interrupt on indication from the HDCP Receiver.
Allows propagation of interrupts from downstream devices.
IE_LIST_RDY Interrupt on KSV List Ready: Enables interrupt on KSV List Ready.
IE_KSV_RDY Interrupt on KSV Ready: Enables interrupt on KSV Ready.
IE_AUTH_FAI Interrupt on Authentication Failure: Enables interrupt on authentication failure or loss of
L
authentication.
IE_AUTH_PAS Interrupt on Authentication Pass: Enables interrupt on successful completion of
S
authentication.
INT_EN
Global Interrupt Enable: Enables interrupt on the interrupt signal to the controller.
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