DS90UH929-Q1 Datasheet, PDF (24/77 Pages) Texas Instruments – 720p HDMI to FPD-Link III Bridge Serializer with HDCP

DS90UH929-Q1
SNLS458 – NOVEMBER 2014
I2S_WC
t1/fS (256 BCKs at Single Rate, 128 BCKs at Dual Rate)t
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I2S_CLK
I²S Mode
DIN1
(Single)
Ch 1
t32 BCKst
23 22 0
Ch 2
t32 BCKst
23 22 0
Ch 3
t32 BCKst
23 22 0
Ch 4
t32 BCKst
23 22 0
Ch 5
t32 BCKst
23 22 0
Ch 6
t32 BCKst
23 22 0
Ch 7
t32 BCKst
23 22 0
Ch 8
t32 BCKst
23 22 0
23 22
Figure 13. TDM Format
8.3.17 HDCP
The HDCP Cipher function is implemented in the serializer per HDCP v1.4 specification. The serializer provides
HDCP encryption of audiovisual content when connected to an HDCP capable source. HDCP authentication and
shared key generation is performed using the HDCP Control Channel, which is embedded in the forward and
backward channels of the serial link. On-chip Non-Volatile Memory (NVM) is used to store the HDCP keys. The
confidential HDCP keys are loaded by TI during the manufacturing process and are not accessible external to the
device.
8.3.17.1 HDCP I2S Audio Encryption
Depending on the quality and specifications of the audiovisual source, HDCP encryption of digital audio may be
required. When HDCP is active, packetized Data Island Transport audio is also encrypted along with the video
data per HDCP v.1.4. I2S audio transmitted in Forward Channel Frame Transport mode is not encrypted. System
designers should consult the specific HDCP specifications to determine if encryption of digital audio is required
by the specific application audiovisual source.
8.3.18 Built In Self Test (BIST)
An optional At-Speed Built-In Self Test (BIST) feature supports testing of the high speed serial link and back
channel without external data connections. This is useful in the prototype stage, equipment production, in-system
test, and system diagnostics.
8.3.18.1 BIST Configuration And Status
The BIST mode is enabled at the deserializer by pin (BISTEN) or BIST configuration register. The test may
select either an external TMDS clock or the internal Oscillator clock (OSC) frequency. In the absence of TMDS
clock, the user can select the internal OSC frequency at the deserializer through the BISTC pin or BIST
configuration register.
When BIST is activated at the deserializer, a BIST enable signal is sent to the serializer through the Back
Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test
pattern and monitors it for errors. The deserializer PASS output pin toggles to flag each frame received
containing one or more errors. The serializer also tracks errors indicated by the CRC fields in each back channel
frame.
The BIST status can be monitored real time on the deserializer PASS pin, with each detected error resulting in a
half pixel clock period toggled LOW. After BIST is deactivated, the result of the last test is held on the PASS
output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low
on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width
applied to the deserializer BISTEN pin. LOCK is valid throughout the entire duration of BIST.
See Figure 14 for the BIST mode flow diagram.
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