DS90UH929-Q1 Datasheet, PDF (42/77 Pages) Texas Instruments – 720p HDMI to FPD-Link III Bridge Serializer with HDCP

DS90UH929-Q1
SNLS458 – NOVEMBER 2014
www.ti.com
Register Maps (continued)
ADD
(dec)
31
ADD
(hex)
0x1F
Register Name
Frequency
Counter
32
0x20 Deserializer
Capabilities 1
Bit(s)
7:0
7
6
5
4
3
2
Table 8. Serial Control Bus Registers (continued)
Register
Type
RW
RW
RW
RW
RW
Default
(hex)
0x00
0x00
0x00
Function
Description
Frequency
Count
Frequency counter control.
A write to this register will enable a frequency counter to count the number of pixel clock
during a specified time interval. The time interval is equal to the value written multiplied
by the oscillator clock period (nominally 40ns). A read of the register returns the number
of pixel clock edges seen during the enabled interval. The frequency counter will freeze
at 0xff if it reaches the maximum value. The frequency counter will provide a rough
estimate of the pixel clock period. If the pixel clock frequency is known, the frequency
counter may be used to determine the actual oscillator clock frequency.
FREEZE_DES Freeze Deserializer Capabilities.
_CAP
Prevent auto-loading of the Deserializer Capabilities by the Bidirectional Control Channel.
The Capabilities will be frozen at the values written in registers 0x20 and 0x21.
Reserved.
SEND_FREQ
Send Frequency Training Pattern.
Indicates the DS90UH929-Q1 should send the Frequency Training Pattern. This field is
automatically configured by the Bidirectional Control Channel once RX Lock has been
detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit
to prevent overwriting by the Bidirectional Control Channel.
SEND_EQ
Send Equalization Training Pattern.
Indicates the DS90UH929-Q1 should send the Equalization Training Pattern. This field is
automatically configured by the Bidirectional Control Channel once RX Lock has been
detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit
to prevent overwriting by the Bidirectional Control Channel.
DUAL_LINK_C
AP
Dual link Capabilities.
Indicates if the Deserializer is capable of dual link operation. This field is automatically
configured by the Bidirectional Control Channel once RX Lock has been detected.
Software may overwrite this value, but must also set the FREEZE DES CAP bit to
prevent overwriting by the Bidirectional Control Channel.
DUAL_CHANN Dual Channel 0/1 Indication.
EL
In a dual-link capable device, indicates if this is the primary or secondary channel.
0: Primary channel (channel 0).
1: Secondary channel (channel 1).
This field is automatically configured by the Bidirectional Control Channel once RX Lock
has been detected. Software may overwrite this value, but must also set the FREEZE
DES CAP bit to prevent overwriting by the Bidirectional Control Channel.
42
Submit Documentation Feedback
Product Folder Links: DS90UH929-Q1
Copyright © 2014, Texas Instruments Incorporated