DS90UH929-Q1 Datasheet, PDF (44/77 Pages) Texas Instruments – 720p HDMI to FPD-Link III Bridge Serializer with HDCP

DS90UH929-Q1
SNLS458 – NOVEMBER 2014
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Register Maps (continued)
ADD
(dec)
48
ADD
(hex)
0x30
Register Name
SCLK_CTRL
Bit(s)
7
6:5
4:3
2:1
0
49
0x31 AUDIO_CTS0
7:0
50
0x32 AUDIO_CTS1
7:0
51
0x33 AUDIO_CTS2
7:0
52
0x34 AUDIO_N0
7:0
53
0x35 AUDIO_N1
7:0
54
0x36 AUDIO_N2_CO 7:4
EFF
3:0
55
0x37 CLK_CLEAN_ST 7:6
S
5:3
2:0
Table 8. Serial Control Bus Registers (continued)
Register
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
Default
(hex)
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Function
Description
SCLK/WS
SCLK to Word Select Ratio.
0 : 64.
1 : 32.
MCLK/SCLK
MCLK to SCLK Select Ratio.
00 : 4.
01 : 2.
10 : 1.
11 : 8.
CLEAN
CLOCK_DIV
Clock Cleaner divider.
00 : FPD_VCO_CLOCK/8.
01 : FPD_VCO_CLOCK/4.
10 : FPD_VCO_CLOCK/2.
11 : AON_OSC.
CLEAN Mode
If non-zero, the SCLK Input or HDMI N/CTS generated Audio Clock is cleaned digitally
before being used.
00 : Off.
01 : ratio of 1.
10 : ratio of 2.
11 : ratio of 4.
MASTER
If set, the SCLK I/O and the WS_IO are used as an output and the Clock Generation
Circuits are enabled, otherwise they are inputs.
CTS[7:0]
If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO.
CTS[15:8]
If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO.
CTS[23:16] If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO.
N[7:0]
If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO.
N[15:8]
If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO.
COEFF[3:0] Selects the LPF_COEFF in the Clock Cleaner (Feedback is divided by 2^COEFF).
N[19:16]
If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO.
Reserved.
IN_FIFO_LVL Clock Cleaner Input FIFO Level.
OUT_FIFO_LV Clock Cleaner Output FIFO Level.
L
44
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