DS90UH929-Q1 Datasheet, PDF (27/77 Pages) Texas Instruments – 720p HDMI to FPD-Link III Bridge Serializer with HDCP

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DS90UH929-Q1
SNLS458 – NOVEMBER 2014
8.3.19.2 Color Modes
By default, the Pattern Generator operates in 24-bit color mode, where all bits of the Red, Green, and Blue
outputs are enabled. 18-bit color mode can be activated from the configuration registers (Table 8). In 18-bit
mode, the 6 most significant bits (bits 7-2) of the Red, Green, and Blue outputs are enabled; the 2 least
significant bits will be 0.
8.3.19.3 Video Timing Modes
The Pattern Generator has two video timing modes – external and internal. In external timing mode, the Pattern
Generator detects the video frame timing present on the DE and VS inputs. If Vertical Sync signaling is not
present on VS, the Pattern Generator determines Vertical Blank by detecting when the number of inactive pixel
clocks (DE = 0) exceeds twice the detected active line length. In internal timing mode, the Pattern Generator
uses custom video timing as configured in the control registers. The internal timing generation may also be
driven by an external clock. By default, external timing mode is enabled. Internal timing or Internal timing with
External Clock are enabled by the control registers (Table 8).
8.3.19.4 External Timing
In external timing mode, the Pattern Generator passes the incoming DE, HS, and VS signals unmodified to the
video control outputs after a two pixel clock delay. It extracts the active frame dimensions from the incoming
signals in order to properly scale the brightness patterns. If the incoming video stream does not use the VS
signal, the Pattern Generator determines the Vertical Blank time by detecting a long period of pixel clocks without
DE asserted.
8.3.19.5 Pattern Inversion
The Pattern Generator also incorporates a global inversion control, located in the PGCFG register, which causes
the output pattern to be bitwise-inverted. For example, the full screen Red pattern becomes full-screen cyan, and
the Vertically Scaled Black to Green pattern becomes Vertically Scaled White to Magenta.
8.3.19.6 Auto Scrolling
The Pattern Generator supports an Auto-Scrolling mode, in which the output pattern cycles through a list of
enabled pattern types. A sequence of up to 16 patterns may be defined in the registers. The patterns may
appear in any order in the sequence and may also appear more than once.
8.3.19.7 Additional Features
Additional pattern generator features can be accessed through the Pattern Generator Indirect Register Map. It
consists of the Pattern Generator Indirect Address (PGIA reg_0x66 — Table 8) and the Pattern Generator
Indirect Data (PGID reg_0x67 — Table 8). See Application Note AN-2198.
8.3.20 Spread Spectrum Clock Tolerance
The DS90UH929-Q1 (for DVI mode) tolerates a spread spectrum input clock to help reduce EMI. The following
triangular SSC profile is supported:
• Frequency deviation ≤2.5%
• Modulation rate ≤ 100kHz
Note: Maximum frequency deviation and maximum modulation rate are not supported simultaneously. Some
typical examples:
• Frequency deviation: 2.5%, modulation rate: 50kHz
• Frequency deviation: 1.25%, modulation rate: 100kHz
8.4 Device Functional Modes
8.4.1 Mode Select Configuration Settings (MODE_SEL[1:0])
Configuration of the device may be done via the MODE_SEL[1:0] input pins, or via the configuration register bits.
A pull-up resistor and a pull-down resistor of suggested values may be used to set the voltage ratio of the
MODE_SEL[1:0] inputs. See Table 5 and Table 6. These values will be latched into register location during
power-up:
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