DS90UH929-Q1 Datasheet, PDF (45/77 Pages) Texas Instruments – 720p HDMI to FPD-Link III Bridge Serializer with HDCP

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DS90UH929-Q1
SNLS458 – NOVEMBER 2014
Register Maps (continued)
ADD
(dec)
72
ADD
(hex)
0x48
Register Name
APB_CTL
73
0x49 APB_ADR0
74
0x4A APB_ADR1
75
0x4B APB_DATA0
76
0x4C APB_DATA1
77
0x4D APB_DATA2
78
0x4E APB_DATA3
79
0x4F BRIDGE_CTL
Bit(s)
7:5
4:3
2
1
0
7:0
7:0
7:0
7:0
7:0
7:0
7:5
4
3
2
1
0
Table 8. Serial Control Bus Registers (continued)
Register
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
Default
(hex)
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Strap
Function
Description
Reserved.
APB_SELECT
APB Select: Selects target for register access.
00 : HDMI APB interface.
01 : EDID SRAM.
10 : Configuration Data (read only).
11 : Die ID (read only).
APB_AUTO_I APB Auto Increment: Enables auto-increment mode. Upon completion of an APB read or
NC
write, the APB address will automatically be incremented by 0x4 for HDMI registers or by
0x1 for others.
APB_READ
Start APB Read: Setting this bit to a 1 will begin an APB read. Read data will be available
in the APB_DATAx registers. The APB_ADRx registers should be programmed prior to
setting this bit. This bit will be cleared when the read is complete.
APB_ENABLE APB Interface Enable: Set to a 1 to enable the APB interface. The APB_SELECT bits
indicate what device is selected.
APB_ADR0 APB Address byte 0 (LSB).
APB_ADR1 APB Address byte 1 (MSB).
APB_DATA0 Byte 0 (LSB) of the APB Interface Data.
APB_DATA1 Byte 1 of the APB Interface Data.
APB_DATA2 Byte 2 of the APB Interface Data.
APB_DATA3 Byte 3 (MSB) of the APB Interface Data.
Reserved.
CEC_CLK_SR
C
CEC Clock Source Select: Selects clock source for generating the 32.768kHz clock for
CEC operations in the HDMI Receive Controller.
0 : Selects internal generated clock.
1 : Selects external 25MHz oscillator clock.
CEC_CLK_EN CEC Clock Enable: Enable CEC clock generation. Enables generation of the 32.768kHz
clock for the HDMI Receive controller. This bit should be set prior to enabling CEC
operation via the HDMI controller registers.
EDID_CLEAR Clear EDID SRAM: Set to 1 to enable clearing the EDID SRAM. The EDID_INIT bit must
be set at the same time for the clear to occur. This bit will be cleared when the
initialization is complete.
EDID_INIT
Initialize EDID SRAM from EEPROM: Causes a reload of the EDID SRAM from the non-
volatile EDID EEPROM. This bit will be cleared when the initialization is complete.
EDID_DISABL Disable EDID access via DDC/I2C: Disables access to the EDID SRAM via the HDMI
E
DDC interface. This value is loaded from the MODE_SEL0 pin at power-up.
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