DS90UH929-Q1 Datasheet, PDF (22/77 Pages) Texas Instruments – 720p HDMI to FPD-Link III Bridge Serializer with HDCP

DS90UH929-Q1
SNLS458 – NOVEMBER 2014
Table 2. GPIO_REG and GPIO Local Enable and Configuration (continued)
Description
GPIO2
GPIO1
GPIO0
Register Configuration
0x0E[7:4] = 0x1
0x0E[7:4] = 0x9
0x0E[7:4] = 0x3
0x0E[3:0] = 0x1
0x0E[3:0] = 0x9
0x0E[3:0] = 0x3
0x0D[3:0] = 0x1
0x0D[3:0] = 0x9
0x0D[3:0] = 0x3
Function
Output, L
Output, H
Input, Read: 0x1C[2]
Output, L
Output, H
Input, Read: 0x1C[1]
Output, L
Output, H
Input, Read: 0x1C[0]
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8.3.15 Backward Compatibility
This FPD-Link III serializer is backward compatible to the DS90UH926Q-Q1 and DS90UH928Q-Q1 for TMDS
clock frequencies ranging from 25MHz to 85MHz. Backward compatibility does not need to be enabled.
8.3.16 Audio Modes
The DS90UH929-Q1 supports several audio modes and functions:
• HDMI Mode
• DVI Mode
• AUX Audio Channel
8.3.16.1 HDMI Audio
The DS90UH929-Q1 allows embedded audio in the HDMI interface to be transported over the FPD-Link III serial
link and output on the compatible deserializer. Depending on the number of channels, HDMI audio can be output
on several I2S pins on the deserializer, or it can be converted to TDM to output on one audio output pin on the
deserializer.
8.3.16.2 DVI I2S Audio Interface
The DS90UH929-Q1 serializer features six I2S input pins that, when paired with a compatible deserializer,
supports 7.1 High-Definition (HD) Surround Sound audio applications. The bit clock (I2S_CLK) supports
frequencies between 1MHz and the lesser of IN_CLK/2 or 13MHz. Four I2S data inputs transport two channels of
I2S-formatted digital audio each, with each channel delineated by the word select (I2S_WC) input. Refer to
Figure 11 and Figure 12 for I2S connection diagram and timing information.
I2S
Transmitter
Bit Clock
Word Select
Data
4
Serializer
I2S_CLK
I2S_WC
I2S_Dx
Figure 11. I2S Connection Diagram
I2S_WC
I2S_CLK
I2S_Dx
MSB
LSB MSB
LSB
Figure 12. I2S Frame Timing Diagram
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