CC3220MOD_017 Datasheet, PDF (51/100 Pages) Texas Instruments – SimpleLink Wi-Fi CERTIFIED Wireless MCU Modules

www.ti.com
CC3220MOD, CC3220MODA
SWRS206B – MARCH 2017 – REVISED AUGUST 2017
5.14.5.5 IEEE 1149.1 JTAG
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and
boundary scan architecture for digital integrated circuits and provides a standardized serial interface to
control the associated test logic. For detailed information on the operation of the JTAG port and TAP
controller, see the IEEE Standard 1149.1,Test Access Port and Boundary-Scan Architecture.
Figure 5-14 shows the JTAG timing diagram.
T2
T3
T4
TCK
TMS
T7
T8
TMS Input Valid
T7
T8
TMS Input Valid
TDI
T11
TDO
T9
T10
T9
T10
TDI Input Valid
TDI Input Valid
T1
TDO Output Valid
TDO Output Valid
Figure 5-14. JTAG Timing Diagram
Table 5-12 lists the JTAG timing parameters.
Table 5-12. JTAG Timing Parameters
ITEM
NAME
DESCRIPTION
MIN
T1
f_TCK
Clock frequency
T2
t_TCK
Clock period
T3
t_CL
Clock low period
T4
t_CH
Clock high period
T7
t_{TMS_SU}
TMS setup time
1
T8
t_{TMS_HO}
TMS hold time
16
T9
t_{TDI_SU}
TDI setup time
1
T10
t_{TDI_HO}
TDI hold time
16
T11
t_{TDO_HO}
TDO hold time
MAX
15
1 / f_TCK
t_TCK / 2
t_TCK / 2
15
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC3220MOD CC3220MODA
Specifications
51