CC3220MOD_017 Datasheet, PDF (48/100 Pages) Texas Instruments – SimpleLink Wi-Fi CERTIFIED Wireless MCU Modules

CC3220MOD, CC3220MODA
SWRS206B – MARCH 2017 – REVISED AUGUST 2017
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5.14.5.2 I2S
The McASP interface functions as a general-purpose audio serial port optimized for multichannel audio
applications and supports transfer of two stereo channels over two data pins. The McASP consists of
transmit and receive sections that operate synchronously and have programmable clock and frame-sync
polarity. A fractional divider is available for bit-clock generation.
5.14.5.2.1 I2S Transmit Mode
Figure 5-10 shows the timing diagram for the I2S transmit mode.
T2
T1
T3
McACLKX
McAFSX
T4
T4
McAXR0/1
Figure 5-10. I2S Transmit Mode Timing Diagram
Table 5-6 lists the timing parameters for the I2S transmit mode.
Table 5-6. I2S Transmit Mode Timing Parameters
ITEM
NAME
DESCRIPTION
MIN
T1
f_clk ⁽¹⁾
T2
t^{LP (1)}
Clock frequency
Clock low period
T3
t_HT ⁽¹⁾
T4
t_OH ⁽¹⁾
Clock high period
TX data hold time
(1) Timing parameter assumes a maximum load of 20 pF.
5.14.5.2.2 I2S Receive Mode
Figure 5-11 shows the timing diagram for the I2S receive mode.
MAX
9.216
1/2 fclk
1/2 fclk
22
UNIT
MHz
ns
ns
ns
T2
T1
T3
McACLKX
T5
T4
McAFSX
McAXR0/1
Figure 5-11. I2S Receive Mode Timing Diagram
Table 5-7 lists the timing parameters for the I2S receive mode.
Table 5-7. I2S Receive Mode Timing Parameters
ITEM
NAME
DESCRIPTION
MIN
T1
f_clk ⁽¹⁾
T2
t^{LP (1)}
Clock frequency
Clock low period
T3
t_HT ⁽¹⁾
T4
t_OH ⁽¹⁾
T5
t_OS ⁽¹⁾
Clock high period
RX data hold time
RX data setup time
(1) Timing parameter assumes a maximum load of 20 pF.
MAX
9.216
1/2 f_clk
1/2 f_clk
0
15
UNIT
MHz
ns
ns
ns
ns
48
Specifications
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