TL16C554A_13 Datasheet, PDF (5/46 Pages) Texas Instruments – ASYNCHRONOUS-COMMUNICATIONS ELEMENT

functional block diagram (per channel)
Internal
Data ^S
5 − 66 ^Data
Bus
8
e
l
D(7 − 0)
Bus
Buffer
e
c
8
t
Receiver
Buffer
Register
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
Receiver
FIFO
Receiver
Shift
Register
7
RXA
34
A0
A1 ³³
A2 ³²
16
CSA
CSB ²⁰
50
CSC
CSD ⁵⁴
RESET ³⁷
52
IOR
IOW ¹⁸
TXRDY ³⁹
35
XTAL1
36
XTAL2
RXRDY ³⁸
INTN ⁶⁵
Select
and
Control
Logic
Line
Control
Register
Divisor
Latch (LS)
Divisor
Latch (MS)
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Modem
Status
Register
Baud
Generator
Transmitter
S
FIFO
e
l
8
e
c
t
8
8
13, 30, 47, 64
V_CC
6, 23, 40, 57
GND
Power
Supply
Interrupt
Enable
Register
8 ^Interrupt
Control
Logic
Interrupt
8
Identification
Register
FIFO
Control
Register
NOTE A: Terminal numbers shown are for the FN package and channel A.
Receiver
Timing and
Control
Transmitter
Timing and
Control
8 ^Transmitter
Shift
Register
Modem
Control
Logic
14
RTSA
Autoflow
Control
(AFE)
17
TXA
11
CTSA
12
DTRA
10
DSRA
9
DCDA
8
RIA
15 _INTA
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