TL16C554A_13 Datasheet, PDF (20/46 Pages) Texas Instruments – ASYNCHRONOUS-COMMUNICATIONS ELEMENT

TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
PRINCIPLES OF OPERATION
accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 1. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.
Table 3. Summary of Accessible Registers
ADDRES
S
0
0
0^†
1^†
1
REGISTER
MNEMONIC
RBR
(read only)
THR
(write only)
DLL
DLM
IER
BIT 7
Data Bit 7
(MSB)
Data BIt 7
Bit 7
Bit 15
0
BIT 6
Data Bit 6
Data BIt 6
Bit 6
Bit 14
0
2
FCR
Receiver Receiver
(write only) Trigger
Trigger
(MSB)
(LSB)
2
IIR
FIFOs
FIFOs
(read only) Enabled^‡ Enabled^‡
3
LCR
(DLAB) Set break
Divisor
latch
access bit
4
MCR
0
0
5
LSR
Error in
(TEMT)
receiver Transmitter
FIFO^‡
registers
empty
6
MSR
(DCD)
(RI)
Data
Ring
carrier
indicator
detect
7
SCR
Bit 7
Bit 6
† _{DLAB = 1}
‡ _{These bits are always 0 when FIFOs are disabled.}
BIT 5
Data Bit 5
Data BIt 5
Bit 5
Bit 13
0
Reserved
0
Stick parity
Autoflow
control
enable
(AFE)
(THRE)
Transmitter
holding
register
empty
(DSR)
Data set
ready
Bit 5
REGISTER ADDRESS
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Data
Bit 4
Data Bit 3 Data Bit 2
Data Bit 1
Data Bit 0
(LSB)
Data
BIt 4
Data BIt 3 Data BIt 2
Data BIt 1
Data BIt 0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
(EDSSI) (ERLSI)
(ETBEI)
(ERBI)
Enable
Enable
Enable
Enable
modem
receiver
transmitter
received
status line status
holding
data
interrupt interrupt register empty available
interrupt
interrupt
Reserved
DMA
mode
select
Transmit
FIFO reset
Receiver
FIFO reset
FIFO Enable
0
Interrupt Interrupt ID Interrupt ID 0 If interrupt
ID Bit (3)^‡
Bit (2)
Bit (1)
pending
(EPS)
Even-
parity
select
(PEN)
Parity
enable
(STB)
Number of
stop bits
(WLSB1)
Word-length
select bit 1
(WLSB0)
Word-length
select bit 0
Loop
OUT2
Enable
external
interrupt
(INT)
Reserved
(RTS)
Request to
send
(DTR) Data
terminal
ready
(BI)
Break
interrupt
(FE)
Framing
error
(PE)
(OE)
Parity error Overrun error
(DR)
Data ready
(CTS)
Clear to
send
Bit 4
(Δ DCD)
Delta data
carrier
detect
Bit 3
(TERI)
Trailing
edge ring
indicator
Bit 2
(Δ DSR)
Delta data
set ready
Bit 1
(Δ CTS)
Delta
clear to send
Bit 0
20
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