TL16C554A_13 Datasheet, PDF (23/46 Pages) Texas Instruments – ASYNCHRONOUS-COMMUNICATIONS ELEMENT

TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
PRINCIPLES OF OPERATION
interrupt-enable register (IER)
The IER independently enables the four serial channel interrupt sources that activate the interrupt (INTA, B, C,
D) output. All interrupts are disabled by clearing IER0 − IER3 of the IER. Interrupts are enabled by setting the
appropriate bits of the IER. Disabling the interrupt system inhibits the IIR and the active (high) interrupt output.
All other system functions operate in their normal manner, including the setting of the LSR and MSR. The
contents of the IER are shown in Table 3 and described in the following bulleted list:
D Bit 0: When IER0 is set, IER0 enables the received data available interrupt and the timeout interrupts in
the FIFO mode.
D Bit 1: When IER1 is set, the transmitter holding register empty interrupt is enabled.
D Bit 2: When IER2 is set, the receiver line status interrupt is enabled.
D Bit 3: When IER3 is set, the modem-status interrupt is enabled.
D Bits 4 − 7: IER4 − IER7. These four bits of the IER are cleared.
interrupt-identification register (IIR)
In order to minimize software overhead during data character transfers, the serial channel prioritizes interrupts
into four levels as follows:
D Priority 1 − Receiver line status (highest priority)
D Priority 2 − Receiver data ready or receiver character timeout
D Priority 3 −Transmitter holding register empty
D Priority 4 −Modem status (lowest priority)
The IIR stores information indicating that a prioritized interrupt is pending and the type of interrupt. The IIR
indicates the highest priority interrupt pending. The contents of the IIR are indicated in Table 5.
Table 5. Interrupt Control Functions
INTERRUPT
IDENTIFICATION
REGISTER
BIT 3 BIT 2 BIT 1 BIT 0
0
0
0
1
0
1
1
0
0
1
0
0
1
1
0
0
0
0
1
0
0
0
0
0
PRIORITY
LEVEL
—
First
Second
Second
Third
Fourth
INTERRUPT SET AND RESET FUNCTIONS
INTERRUPT TYPE
INTERRUPT SOURCE
None
Receiver line status
Received data available
None
OE, PE, FE, or BI
Receiver data available or
trigger level reached
Character time-out
indicator
THRE
No characters have been
removed from or input to the
receiver FIFO during the last
four character times, and there
is at least one character in it
during this time.
THRE
Modem status
CTS, DSR, RI, or DCD
INTERRUPT
RESET CONTROL
—
LSR read
RBR read until FIFO
drops below the trigger
level
RBR read
IIR read (if THRE is the
interrupt source), or
THR write
MSR read
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
23