TL16C554A_13 Datasheet, PDF (36/46 Pages) Texas Instruments – ASYNCHRONOUS-COMMUNICATIONS ELEMENT

TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
PRINCIPLES OF OPERATION
scratchpad register
The scratchpad register is an 8-bit read/write register that has no effect on any ACE channel. It is intended to
be used by the programmer to hold data temporarily.
TXRDY operation
In mode 0, TXRDY is asserted (low) when the transmit FIFO is empty; it is released (high) when the FIFO
contains at least one byte. In this way, the FIFO is written with 16 bytes when TXRDY is asserted (low).
In mode 1, TXRDY is asserted (low) when the transmit FIFO is not full; in this mode, the transmit FIFO is written
with another byte when TXRDY is asserted (low).
External
Clock
Driver
XTAL1
Optional
Driver
Optional
Clock
Output
XTAL2
V_CC
XTAL1
C1
Crystal
R_P
Oscillator Clock
to Baud
Generator Logic
RX2
XTAL2
C2
V_CC
Oscillator Clock
to Baud
Generator Logic
CRYSTAL
3.1 MHz
1.8 MHz
TYPICAL CRYSTAL OSCILLATOR NETWORK
R_P
1 MΩ
RX2
1.5 kΩ
C1
10 −30 pF
1 MΩ
1.5 kΩ
10 −30 pF
C2
40 −60 pF
40 −60 pF
Figure 24. Typical Clock Circuits
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