TL16C554A_13 Datasheet, PDF (16/46 Pages) Texas Instruments – ASYNCHRONOUS-COMMUNICATIONS ELEMENT

TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
PARAMETER MEASUREMENT INFORMATION
RXx
Sample
Clock
INTx
(time-out or
trigger level)
Interrupt
INTx
Interrupt
IOR
(RD LSR)
Stop
t_d9 (see Note A)
50%
50%
Top Byte of FIFO
50%
t_pd4
50%
t_d9
t_pd4
Active
50%
(FIFO at or above
trigger level)
(FIFO below
trigger level)
IOR
(RD RBR)
Active
50%
Previous BYTE
Read From FIFO
NOTE A: This is the reading of the last byte in the FIFO.
50%
Active
Figure 11. Receiver FIFO After First Byte (After RDR Set) Waveforms
IOR
(RD RBR)
RXx
Stop
50%
Active
(see Note A)
Sample
Clock
t_d9
(see Note B)
RXRDY
50%
50%
t_pd5
NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCR0 = 1, then t_d9 = 3 RCLK cycles. For a time-out interrupt, t_d9 = 8 RCLK cycles.
Figure 12. Receiver Ready Mode 0 Timing Waveforms
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