TL16C554A_13 Datasheet, PDF (35/46 Pages) Texas Instruments – ASYNCHRONOUS-COMMUNICATIONS ELEMENT

TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
PRINCIPLES OF OPERATION
reset
After power up, the ACE RESET input should be held high for one microsecond to reset the ACE circuits to an
idle mode until initialization. A high on RESET causes the following:
1. Initializes the transmitter and receiver internal clock counters.
2. Clears the LSR, except for transmitter register empty (TEMT) and transmit holding register empty (THRE),
which are set. The MCR is also cleared. All of the discrete lines, memory elements, and miscellaneous logic
associated with these register bits are also cleared or turned off. The LCR, divisor latches, RBR, and
transmitter-buffer register are not affected.
RXRDY operation
In mode 0, RXRDY is asserted (low) when the receive FIFO is not empty; it is released (high) when the FIFO
is empty. In this way, the receiver FIFO is read when RXRDY is asserted (low).
In mode 1, RXRDY is asserted (low) when the receive FIFO has filled to the trigger level or a character time-out
has occurred (four character times with no transmission of characters); it is released (high) when the FIFO is
empty. In this mode, many received characters are read by the DMA device, reducing the number of times it
is interrupted.
RXRDY and TXRDY outputs from each of the four internal ACEs of the TL16C554A are ANDed together
internally. This combined signal is brought out externally to RXRDY and TXRDY.
Following the removal of the reset condition (RESET low), the ACE remains in the idle mode until programmed.
A hardware reset of the ACE sets the THRE and TEMT status bits in the LSR. When interrupts are subsequently
enabled, an interrupt occurs due to THRE. A summary of the effect of a reset on the ACE is given in Table 13.
Table 13. RESET Effects on Registers and Signals
REGISTER/SIGNAL
Interrupt-enable register
Interrupt-identification register
Line-control register
Modem-control register
FIFO-control register
Line-status register
Modem-status register
TXx
Interrupt (RCVR ERRS)
Interrupt (receiver data ready)
Interrupt (THRE)
Interrupt (modem status changes)
RTS
DTR
RESET CONTROL
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Read LSR/reset
Read RBR/reset
Read IIR/write THR/reset
Read MSR/reset
Reset
Reset
RESET STATE
All bits cleared (0 −3 forced and 4 −7 permanent)
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared,
Bits 4 −5 are permanently cleared
All bits cleared
All bits cleared (5 −7 permanent)
All bits cleared
All bits cleared, except bits 5 and 6 are set
Bits 0 −3 cleared, bits 4 −7 input signals
High
Low
Low
Low
Low
High
High
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