TL16C554A_13 Datasheet, PDF (10/46 Pages) Texas Instruments – ASYNCHRONOUS-COMMUNICATIONS ELEMENT

TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
read cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 4)
MIN MAX UNIT
t_w4
Pulse duration, IOR low
75
ns
t_su1
Setup time, CSx valid before IOR low (see Note 2)
10
ns
t_su2
Setup time, A2 −A0 valid before IOR low (see Note 2)
15
ns
t_h1
Hold time, A2 −A0 valid after IOR high (see Note 2)
0
ns
t_h2
Hold time, CSx valid after IOR high (see Note 2)
0
ns
t_d1
Delay time, t_su2 + t_w4 + t_d2 (see Note 3)
140
ns
t_d2
Delay time, IOR high to IOR or IOW low
50
ns
NOTES: 2. The internal address strobe is always active.
3. In the FIFO mode, t_d1 = 425 ns (min) between reads of the receiver FIFO and the status registers (interrupt-identification register
and line-status register).
write cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 5)
t_w5
Pulse duration, IOW↓
t_su3 Setup time, CSx valid before IOW↓ (see Note 2)
t_su4 Setup time, A2 −A0 valid before IOW↓ (see Note 2)
t_su5 Setup time, D7 −D0 valid before IOW↑
t_h3
Hold time, A2 −A0 valid after IOW↑ (see Note 2)
t_h4
Hold time, CSx valid after IOW↑ (see Note 2)
t_h5
Hold time, D7 −D0 valid after IOW↑
t_d3
Delay time, t_su4 + t_w5 + t_d4
t_d4
Delay time, IOW↑ to IOW or IOR↓
NOTE 2: The internal address strobe is always active.
MIN MAX UNIT
50
ns
10
ns
15
ns
10
ns
5
ns
5
ns
25
ns
120
ns
55
ns
read cycle switching characteristics over recommended ranges of operating free-air temperature
and supply voltage, C_L = 100 pF (see Note 4 and Figure 4)
PARAMETER
MIN MAX UNIT
t_en
Enable time, IOR↓ to D7 −D0 valid
t_dis
Disable time, IOR↑ to D7 −D0 released
NOTE 4: V_OL and V_OH (and the external loading) determine the charge and discharge time.
30 ns
0
20 ns
10
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