TL16C554A_13 Datasheet, PDF (17/46 Pages) Texas Instruments – ASYNCHRONOUS-COMMUNICATIONS ELEMENT

TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
PARAMETER MEASUREMENT INFORMATION
IOR
(RD RBR)
SIN
(first byte that reaches
the trigger level)
Sample
Clock
Stop
50%
Active
(see Note A)
t_d9
(see Note B)
RXRDY
50%
50%
t_pd5
NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCR0 = 1, t_d9 = 3 RCLK cycles. For a trigger change level interrupt, t_d9 = 8 RCLK.
Figure 13. Receiver Ready Mode 1 Timing Waveforms
IOW
(WR MCR)
RTSx, DTRx
CTSx, DSRx,
DCDx
INTx
50%
t_pd6
50%
50%
t_pd7
50%
50%
t_pd7
50%
50%
t_pd6
50%
50%
50%
t_pd8
t_pd9
IOR
(RD MSR)
50%
RIx
50%
Figure 14. Modem Control Timing Waveforms
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
17