DS90UA101-Q1 Datasheet, PDF (5/42 Pages) Texas Instruments – DS90UA101-Q1 Multi-Channel Digital Audio Link

DS90UA101-Q1
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Pin Name
PDB
Pin #
9
Serial Interface
DOUT+
13
DOUT-
12
Power and Ground
VDDPLL
10
VDDT
11
VDDCML
14
VDDIO
25
VDDD
28
GND
DAP
Other
RES0
7
SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013
I/O, Type
Description
Input, LVCMOS w/
pull down
Power down mode input pin.
PDB = H, device is enabled and is ON.
PDB = L, device is powered down.
When the device is in the powered down state, the transmitter outputs are both HIGH,
the PLL is shutdown, and IDD is minimized. Control registers are RESET.
Input/Output, LVDS True serial interface output.
The interconnection must be AC-coupled to this pin with a 0.1 µF capacitor.
Input/Output, LVDS Inverting serial interface output.
The interconnection must be AC-coupled to this pin with a 0.1 µF capacitor.
Power
Power
Power
Power
Power
Ground
1.8V (±5%) PLL power.
1.8V (±5%) analog core power.
1.8V (±5%) CML driver power.
LVCMOS I/O power. 1.8V (±5%) or 3.3V (±10%).
1.8V (±5%) digital power.
DAP is the large metal contact located at the bottom center of the LLP package.
Connect to the GND plane with at least 9 vias.
Reserved
Reserved.
Connect to GND.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2013, Texas Instruments Incorporated
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