DS90UA101-Q1 Datasheet, PDF (25/42 Pages) Texas Instruments – DS90UA101-Q1 Multi-Channel Digital Audio Link

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LRCK
DS90UA101-Q1
SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013
t1/fS (256 BCKs at Single Rate, 128 BCKs at Dual Rate)t
BCK
I²S Mode
DIN1
(Single)
Ch 1
t32 BCKst
23 22 0
Ch 2
t32 BCKst
23 22 0
Ch 3
t32 BCKst
23 22 0
Ch 4
t32 BCKst
23 22 0
Ch 5
t32 BCKst
23 22 0
Ch 6
t32 BCKst
23 22 0
Ch 7
t32 BCKst
23 22 0
Ch 8
t32 BCKst
23 22 0
23 22
Figure 19. TDM Format
Error Detection
The chipset provides error detection operations for validating data integrity in long distance transmission and
reception. The data error detection function offers users flexibility and usability of performing bit-by-bit data
transmission error checking. The error detection operating modes support data validation of the following signals:
• Bidirectional Control Channel data across the serial link
• Parallel audio/sync data across the serial link
The chipset provides 1 parity bit on the forward channel and 4 CRC bits on the back channel for error detection
purposes. The DS90UA101-Q1/DS90UA102-Q1 chipset checks the forward and back channel serial links for
errors and stores the number of detected errors in two 8-bit registers in the Serializer and the Deserializer,
respectively.
To check parity errors on the forward channel, monitor registers 0x1A and 0x1B on the Deserializer. If there is a
loss of LOCK, then the counters on registers 0x1A and 0x1B are reset. Whenever there is a parity error on the
forward channel, the PASS pin will go low momentarily.
To check CRC errors on the back-channel, monitor registers 0x0A and 0x0B on the Serializer.
Bidirectional Control Bus and I²C
The I²C compatible interface allows programming of the Serializer, Deserializer, or an external remote device
through the Bidirectional Control Channel. For example, an audio module connected to the Deserializer can
communicate with the ADC connected to the Serializer using the Bidirectional Control Channel. Register
programming transactions to/from the chipset are employed through the clock (SCL) and data (SDA) lines. These
two signals have open drain I/Os and both lines must be pulled-up to V_DDIO by an external resistor. Pull-up
resistors or current sources are required on the SCL and SDA busses to pull them high when they are not being
driven low. A logic LOW is transmitted by driving the output low. Logic HIGH is transmitted by releasing the
output and allowing it to be pulled-up externally. The appropriate pull-up resistor values will depend upon the
total bus capacitance and operating speed. The DS90UA101-Q1/DS90UA102-Q1 I²C bus data rate supports up
to 400 kbps according to I²C fast mode specifications. Figure 20, Figure 21, Figure 22, Figure 23 show I²C
waveforms of read/write bytes, basic operation, and start/stop conditions.
N
Bus Activity:
A
Master
Slave
Register
Slave
C
Address
Address
Address
K
SDA Line S
7-bit Address 0
S
7-bit Address 1
P
Bus Activity:
Slave
A
A
C
C
K
K
Figure 20. Read Byte
A
Data
C
K
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