DS90UA101-Q1 Datasheet, PDF (13/42 Pages) Texas Instruments – DS90UA101-Q1 Multi-Channel Digital Audio Link

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DS90UA101-Q1
SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013
TIMING AND CIRCUIT DIAGRAMS
SDA
t_f
SCL
START
t_LOW
t_r
t_f
t_HD;STA
t_BUF
t_r
t_HD;STA
t_HD;DAT
t_HIGH
t_SU;DAT
t_SU;STA
t_SU;STO
REPEATED
START
Figure 4. Bidirectional Control Bus Timing
STOP START
T
SCK
(RFB = H)
DIN[7:0]
Figure 5. "Worst Case" Test Pattern
Vdiff
80%
20%
80%
Vdiff = 0V
20%
t_LHT
t_HLT
Vdiff = (DOUT+) - (DOUT-)
Figure 6. Serializer CML Output Transition Times
DOUT+ ^{0.1 µF}
DOUT-
0.1 µF
Z_Diff = 1003
503
1003
503
SCOPE
BW & 4.0 GHz
Figure 7. Serializer CML Output Load
Single-Ended
DOUT-
VOD
DOUT+
V_OD+
V_OD-
§ V_OS
Differential
V_OD+
(DOUT+) - (DOUT-)
0V
V_OD-
Figure 8. Serializer VOD and Differential Diagram
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